Lines Matching +full:tx +full:- +full:fifo +full:- +full:max +full:- +full:num
1 /* SPDX-License-Identifier: GPL-2.0 */
38 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
39 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
40 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
41 #define GREG_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
42 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
45 #define GREG_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
46 #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
47 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
48 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
49 #define GREG_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
50 #define GREG_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
51 #define GREG_STAT_DTIMEXP 0x00008000 /* Defer-timer expired */
52 #define GREG_STAT_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
60 #define GREG_STAT_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
61 #define GREG_STAT_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */
75 #define GREG_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */
76 #define GREG_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */
77 #define GREG_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */
78 #define GREG_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */
79 #define GREG_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */
82 #define GREG_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
83 #define GREG_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error */
84 #define GREG_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */
85 #define GREG_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */
86 #define GREG_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */
87 #define GREG_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */
88 #define GREG_IMASK_DTIMEXP 0x00008000 /* Defer-timer expired */
89 #define GREG_IMASK_RXTOHOST 0x00010000 /* Moved from receive-FIFO to host memory */
97 #define GREG_IMASK_HOSTTOTX 0x01000000 /* Moved from host memory to transmit-FIFO */
98 #define GREG_IMASK_TXALL 0x02000000 /* Transmitted all packets in the tx-fifo */
112 #define ETX_FIFOWPTR 0x14UL /* FIFO write ptr */
113 #define ETX_FIFOSWPTR 0x18UL /* FIFO write ptr (shadow register) */
114 #define ETX_FIFORPTR 0x1cUL /* FIFO read ptr */
115 #define ETX_FIFOSRPTR 0x20UL /* FIFO read ptr (shadow register) */
116 #define ETX_FIFOPCNT 0x24UL /* FIFO packet counter */
127 #define ETX_CFG_FIFOTHRESH 0x000003fe /* Transmit FIFO threshold */
128 #define ETX_CFG_IRQDAFTER 0x00000400 /* Interrupt after TX-FIFO drained */
129 #define ETX_CFG_IRQDBEFORE 0x00000000 /* Interrupt before TX-FIFO drained */
137 #define ERX_FIFOWPTR 0x0cUL /* FIFO write ptr */
138 #define ERX_FIFOSWPTR 0x10UL /* FIFO write ptr (shadow register) */
139 #define ERX_FIFORPTR 0x14UL /* FIFO read ptr */
140 #define ERX_FIFOSRPTR 0x18UL /* FIFO read ptr (shadow register) */
159 /* 0x4-->0x204, reserved */
162 #define BMAC_IGAP1 0x210UL /* Inter-packet gap 1 */
163 #define BMAC_IGAP2 0x214UL /* Inter-packet gap 2 */
170 #define BMAC_TXMAX 0x230UL /* Transmit max pkt size */
174 #define BMAC_NCCTR 0x240UL /* Transmit normal-collision counter */
175 #define BMAC_FCCTR 0x244UL /* Transmit first-collision counter */
176 #define BMAC_EXCTR 0x248UL /* Transmit excess-collision counter */
177 #define BMAC_LTCTR 0x24cUL /* Transmit late-collision counter */
180 /* 0x258-->0x304, reserved */
183 #define BMAC_RXMAX 0x310UL /* Receive max pkt size */
189 #define BMAC_GLECTR 0x328UL /* Receive giant-length error counter */
207 #define BIGMAC_XCFG_XLBACK 0x00000002 /* Loopback-mode XIF enable */
208 #define BIGMAC_XCFG_MLBACK 0x00000004 /* Loopback-mode MII enable */
221 #define BIGMAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
265 #define TCV_STAT_NORMAL 0x0000ffff /* The "non-basic" part */
286 #define CSCONFIG_LED4 0x0002 /* Pin for full-dplx LED4 */
287 #define CSCONFIG_LED1 0x0004 /* Pin for conn-status LED1 */
294 #define CSCONFIG_ENCODE 0x0800 /* 1=MLT-3, 0=binary */
326 #define TXFLAG_CSENABLE 0x10000000 /* 1 = enable hw-checksums */
360 #define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1)) argument
361 #define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1)) argument
362 #define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1)) argument
363 #define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1)) argument
366 (((hp)->tx_old <= (hp)->tx_new) ? \
367 (hp)->tx_old + (TX_RING_SIZE - 1) - (hp)->tx_new : \
368 (hp)->tx_old - (hp)->tx_new - 1)
381 ((__u32)((unsigned long)(&(((struct hmeal_init_block *)0)->mem[elem]))))
393 lupwait = 1, /* Auto-neg complete, awaiting link-up status. */
403 struct hmeal_init_block *happy_block; /* RX and TX descriptors (CPU addr) */
447 unsigned int auto_speed; /* Auto-nego link speed */
454 unsigned int lnkcnt; /* Counter for link-up attempts. */
456 enum happy_timer_state timer_state; /* State of the auto-neg timer. */
466 #define HFLAG_LANCE 0x00000004 /* We are using lance-mode */
468 #define HFLAG_AUTO 0x00000010 /* Using auto-negotiation, 0 = force */
498 ((((unsigned long)(addr) + (64UL - 1UL)) & ~(64UL - 1UL)) - (unsigned long)(addr))
503 int __offset = (int) ALIGNED_RX_SKB_ADDR(__skb->data); \