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/linux-6.12.1/drivers/gpu/drm/tegra/
Dmipi-phy.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "mipi-phy.h"
12 * Default D-PHY timings based on MIPI D-PHY specification. Derived from the
13 * valid ranges specified in Section 6.9, Table 14, Page 40 of the D-PHY
16 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, in mipi_dphy_timing_get_default() argument
19 timing->clkmiss = 0; in mipi_dphy_timing_get_default()
20 timing->clkpost = 70 + 52 * period; in mipi_dphy_timing_get_default()
21 timing->clkpre = 8; in mipi_dphy_timing_get_default()
22 timing->clkprepare = 65; in mipi_dphy_timing_get_default()
23 timing->clksettle = 95; in mipi_dphy_timing_get_default()
[all …]
/linux-6.12.1/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
8 #include <dt-bindings/phy/phy.h>
13 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
20 v = (tmax - tmin) * percent; in linear_inter()
22 if (even && (v & 0x1)) in linear_inter()
23 return max_t(s32, min_result, v - 1); in linear_inter()
28 static void dsi_dphy_timing_calc_clk_zero(struct msm_dsi_dphy_timing *timing, in dsi_dphy_timing_calc_clk_zero() argument
35 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui; in dsi_dphy_timing_calc_clk_zero()
36 tmin = S_DIV_ROUND_UP(temp, ui) - 2; in dsi_dphy_timing_calc_clk_zero()
[all …]
Ddsi_phy_20nm.c1 // SPDX-License-Identifier: GPL-2.0-only
11 struct msm_dsi_dphy_timing *timing) in dsi_20nm_dphy_set_timing() argument
13 void __iomem *base = phy->base; in dsi_20nm_dphy_set_timing()
15 writel(DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero), in dsi_20nm_dphy_set_timing()
17 writel(DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail), in dsi_20nm_dphy_set_timing()
19 writel(DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare), in dsi_20nm_dphy_set_timing()
21 if (timing->clk_zero & BIT(8)) in dsi_20nm_dphy_set_timing()
24 writel(DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit), in dsi_20nm_dphy_set_timing()
26 writel(DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero), in dsi_20nm_dphy_set_timing()
28 writel(DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare), in dsi_20nm_dphy_set_timing()
[all …]
/linux-6.12.1/drivers/clk/tegra/
Dclk-tegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/tegra/clk-emc.c
11 #include <linux/clk-provider.h>
29 #define CLK_SOURCE_EMC 0x19c
31 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_SHIFT 0
32 #define CLK_SOURCE_EMC_EMC_2X_CLK_DIVISOR_MASK 0xff
37 #define CLK_SOURCE_EMC_EMC_2X_CLK_SRC_MASK 0x7
48 * When we change the timing to a timing with a parent that has the same
50 * timing that has a different clock source.
53 #define EMC_SRC_PLL_M 0
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/link/
Dlink_validation.c27 * This file owns timing validation against various link limitations. (ex.
38 static uint32_t get_tmds_output_pixel_clock_100hz(const struct dc_crtc_timing *timing) in get_tmds_output_pixel_clock_100hz() argument
41 uint32_t pxl_clk = timing->pix_clk_100hz; in get_tmds_output_pixel_clock_100hz()
43 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) in get_tmds_output_pixel_clock_100hz()
45 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) in get_tmds_output_pixel_clock_100hz()
48 if (timing->display_color_depth == COLOR_DEPTH_101010) in get_tmds_output_pixel_clock_100hz()
50 else if (timing->display_color_depth == COLOR_DEPTH_121212) in get_tmds_output_pixel_clock_100hz()
57 const struct dc_crtc_timing *timing, in dp_active_dongle_validate_timing() argument
60 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps; in dp_active_dongle_validate_timing()
62 switch (dpcd_caps->dongle_type) { in dp_active_dongle_validate_timing()
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/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dtiming.c26 #include <subdev/bios/timing.h>
33 u32 timing = 0; in nvbios_timingTe() local
37 timing = nvbios_rd32(bios, bit_P.offset + 4); in nvbios_timingTe()
40 timing = nvbios_rd32(bios, bit_P.offset + 8); in nvbios_timingTe()
42 if (timing) { in nvbios_timingTe()
43 *ver = nvbios_rd08(bios, timing + 0); in nvbios_timingTe()
45 case 0x10: in nvbios_timingTe()
46 *hdr = nvbios_rd08(bios, timing + 1); in nvbios_timingTe()
47 *cnt = nvbios_rd08(bios, timing + 2); in nvbios_timingTe()
48 *len = nvbios_rd08(bios, timing + 3); in nvbios_timingTe()
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/linux-6.12.1/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_encoder_phys_vid.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
18 (e) && (e)->parent ? \
19 (e)->parent->base.id : -1, \
20 (e) && (e)->hw_intf ? \
21 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
24 (e) && (e)->parent ? \
25 (e)->parent->base.id : -1, \
26 (e) && (e)->hw_intf ? \
27 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
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/linux-6.12.1/drivers/video/fbdev/
Dgbefb.c4 * Copyright (C) 1999 Silicon Graphics, Inc. - Jeffrey Newquist
5 * Copyright (C) 2002 Vivien Chappelier <vivien.chappelier@linux-mips.org>
14 #include <linux/dma-mapping.h>
37 struct gbe_timing_info timing; member
42 #define GBE_BASE 0x16000000 /* SGI O2 */
44 /* macro for fastest write-though access to the framebuffer */
63 #define TILE_MASK (TILE_SIZE - 1)
81 static int gbe_turned_on; /* 0 turned off, 1 turned on */
87 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
92 .xoffset = 0,
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/linux-6.12.1/drivers/video/fbdev/via/
Dvia_modesetting.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
12 #include <linux/via-core.h>
18 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
22 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
23 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
24 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
25 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
26 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
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/linux-6.12.1/drivers/memory/tegra/
Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
15 #include <linux/interconnect-provider.h>
31 #define EMC_FBIO_CFG5 0x104
32 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
33 #define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
36 #define EMC_INTSTATUS 0x0
39 #define EMC_CFG 0xc
44 #define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
47 #define EMC_REFCTRL 0x20
[all …]
Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
40 #define EMC_INTSTATUS 0x000
41 #define EMC_INTMASK 0x004
42 #define EMC_DBG 0x008
43 #define EMC_ADR_CFG 0x010
44 #define EMC_CFG 0x00c
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dsc/
Ddc_dsc.c52 /* Need to account for padding due to pixel-to-symbol packing
56 const struct dc_crtc_timing *timing, const uint32_t kbps) in apply_128b_132b_stream_overhead() argument
63 if (!timing->flags.DSC) { in apply_128b_132b_stream_overhead()
68 bpp = dc_fixpt_div_int(bpp, timing->pix_clk_100hz / 10); in apply_128b_132b_stream_overhead()
70 /* Symbols_per_HActive = HActive * bpp / (4 lanes * 32-bit symbol size) in apply_128b_132b_stream_overhead()
73 overhead_factor = dc_fixpt_from_int(timing->h_addressable); in apply_128b_132b_stream_overhead()
88 const struct dc_crtc_timing *timing, in dc_bandwidth_in_kbps_from_timing() argument
91 uint32_t bits_per_channel = 0; in dc_bandwidth_in_kbps_from_timing()
94 if (timing->flags.DSC) in dc_bandwidth_in_kbps_from_timing()
95 return dc_dsc_stream_bandwidth_in_kbps(timing, in dc_bandwidth_in_kbps_from_timing()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/
Ddml21_translation_helper.c1 // SPDX-License-Identifier: MIT
22 switch (in_dc->ctx->dce_version) { in dml21_init_socbb_params()
23 …case DCN_VERSION_3_2: // TODO : Temporary for N-1 validation. Remove this after N-1 validation pha… in dml21_init_socbb_params()
29 if (config->bb_from_dmub) in dml21_init_socbb_params()
30 soc_bb = config->bb_from_dmub; in dml21_init_socbb_params()
38 memcpy(&dml_init->soc_bb, soc_bb, sizeof(struct dml2_soc_bb)); in dml21_init_socbb_params()
41 memcpy(&dml_init->soc_bb.qos_parameters, qos_params, sizeof(struct dml2_soc_qos_parameters)); in dml21_init_socbb_params()
47 memcpy(&dml_init->soc_bb, &config->external_socbb_ip_params->soc_bb, sizeof(struct dml2_soc_bb)); in dml21_external_socbb_params()
53 …memcpy(&dml_init->ip_caps, &config->external_socbb_ip_params->ip_params, sizeof(struct dml2_ip_cap… in dml21_external_ip_params()
62 switch (in_dc->ctx->dce_version) { in dml21_init_ip_params()
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/linux-6.12.1/drivers/gpu/drm/sti/
Dsti_awg_utils.c1 // SPDX-License-Identifier: GPL-2.0
11 #define AWG_DELAY (-5)
14 #define AWG_MAX_ARG 0x3ff
34 u32 instruction = 0; in awg_generate_instr()
35 u32 mux = (mux_sel << 8) & 0x1ff; in awg_generate_instr()
36 u32 data_enable = (data_en << 9) & 0x2ff; in awg_generate_instr()
46 while (arg_tmp > 0) { in awg_generate_instr()
48 if (fwparams->instruction_offset >= AWG_MAX_INST) { in awg_generate_instr()
50 return -EINVAL; in awg_generate_instr()
57 arg--; /* pixel adjustment */ in awg_generate_instr()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/optc/dcn201/
Ddcn201_optc.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
32 optc1->tg_regs->reg
35 optc1->base.ctx
39 optc1->tg_shift->field_name, optc1->tg_mask->field_name
45 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc201_triplebuffer_lock()
46 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); in optc201_triplebuffer_lock()
47 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc201_triplebuffer_lock()
49 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc201_triplebuffer_lock()
61 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc201_triplebuffer_unlock()
62 OTG_MASTER_UPDATE_LOCK, 0); in optc201_triplebuffer_unlock()
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/linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
Dramnv50.c34 #include <subdev/bios/timing.h>
71 #define T(t) cfg->timing_10_##t
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
75 struct nvbios_ramcfg *cfg = &ram->base.target.bios; in nv50_ram_timing_calc()
76 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv50_ram_timing_calc()
77 struct nvkm_device *device = subdev->device; in nv50_ram_timing_calc()
81 cur2 = nvkm_rd32(device, 0x100228); in nv50_ram_timing_calc()
82 cur4 = nvkm_rd32(device, 0x100230); in nv50_ram_timing_calc()
83 cur7 = nvkm_rd32(device, 0x10023c); in nv50_ram_timing_calc()
84 cur8 = nvkm_rd32(device, 0x100240); in nv50_ram_timing_calc()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_timing_generator_v.c42 tg->ctx->logger
45 * DCE11 Timing Generator Implementation
56 * Set MASTER_UPDATE_MODE to 0 in dce110_timing_generator_v_enable_crtc()
61 value = 0; in dce110_timing_generator_v_enable_crtc()
62 set_reg_field_value(value, 0, in dce110_timing_generator_v_enable_crtc()
64 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
68 value = 0; in dce110_timing_generator_v_enable_crtc()
69 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
71 value = 0; in dce110_timing_generator_v_enable_crtc()
74 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
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/linux-6.12.1/drivers/media/rc/img-ir/
Dimg-ir-hw.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright 2010-2014 Imagination Technologies Ltd.
12 #include <media/rc-core.h>
16 #define IMG_IR_CODETYPE_PULSELEN 0x0 /* Sony */
17 #define IMG_IR_CODETYPE_PULSEDIST 0x1 /* NEC, Toshiba, Micom, Sharp */
18 #define IMG_IR_CODETYPE_BIPHASE 0x2 /* RC-5/6 */
19 #define IMG_IR_CODETYPE_2BITPULSEPOS 0x3 /* RC-MM */
22 /* Timing information */
25 * struct img_ir_control - Decoder control settings
53 * struct img_ir_timing_range - range of timing values
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/linux-6.12.1/Documentation/devicetree/bindings/mmc/
Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
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/linux-6.12.1/drivers/leds/
Dleds-expresswire.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/leds-expresswire.h>
18 gpiod_set_value_cansleep(props->ctrl_gpio, 0); in expresswire_power_off()
19 usleep_range(props->timing.poweroff_us, props->timing.poweroff_us * 2); in expresswire_power_off()
25 gpiod_set_value(props->ctrl_gpio, 1); in expresswire_enable()
26 udelay(props->timing.detect_delay_us); in expresswire_enable()
27 gpiod_set_value(props->ctrl_gpio, 0); in expresswire_enable()
28 udelay(props->timing.detect_us); in expresswire_enable()
29 gpiod_set_value(props->ctrl_gpio, 1); in expresswire_enable()
35 gpiod_set_value(props->ctrl_gpio, 1); in expresswire_start()
[all …]
/linux-6.12.1/drivers/ata/
Dpata_triflex.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * pata_triflex.c - Compaq PATA for new ATA layer
15 * Copyright (C) 2002 Hewlett-Packard Development Group, L.P.
36 * triflex_prereset - probe begin
46 { 0x80, 1, 0x01, 0x01 }, in triflex_prereset()
47 { 0x80, 1, 0x02, 0x02 } in triflex_prereset()
50 struct ata_port *ap = link->ap; in triflex_prereset()
51 struct pci_dev *pdev = to_pci_dev(ap->host->dev); in triflex_prereset()
53 if (!pci_test_config_bits(pdev, &triflex_enable_bits[ap->port_no])) in triflex_prereset()
54 return -ENOENT; in triflex_prereset()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/resource/dcn32/
Ddcn32_resource_helpers.c44 struct hubp *hubp = pipe_ctx->plane_res.hubp; in dcn32_helper_calculate_mall_bytes_for_cursor()
45 uint32_t cursor_size = hubp->curs_attr.pitch * hubp->curs_attr.height; in dcn32_helper_calculate_mall_bytes_for_cursor()
46 uint32_t cursor_mall_size_bytes = 0; in dcn32_helper_calculate_mall_bytes_for_cursor()
48 switch (pipe_ctx->stream->cursor_attributes.color_format) { in dcn32_helper_calculate_mall_bytes_for_cursor()
67 if (pipe_ctx->stream->cursor_position.enable && (ignore_cursor_buf || in dcn32_helper_calculate_mall_bytes_for_cursor()
72 cursor_mall_size_bytes = ((cursor_size + DCN3_2_MALL_MBLK_SIZE_BYTES - 1) / in dcn32_helper_calculate_mall_bytes_for_cursor()
94 if (context->bw_ctx.bw.dcn.mall_subvp_size_bytes > 0) { in dcn32_helper_calculate_num_ways_for_subvp()
95 if (dc->debug.force_subvp_num_ways) { in dcn32_helper_calculate_num_ways_for_subvp()
96 return dc->debug.force_subvp_num_ways; in dcn32_helper_calculate_num_ways_for_subvp()
97 } else if (dc->res_pool->funcs->calculate_mall_ways_from_bytes) { in dcn32_helper_calculate_num_ways_for_subvp()
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/
Ddml2_mall_phantom.c1 /* SPDX-License-Identifier: MIT */
34 uint32_t num_ways = 0; in dml2_helper_calculate_num_ways_for_subvp()
35 uint32_t bytes_per_pixel = 0; in dml2_helper_calculate_num_ways_for_subvp()
36 uint32_t cache_lines_used = 0; in dml2_helper_calculate_num_ways_for_subvp()
37 uint32_t lines_per_way = 0; in dml2_helper_calculate_num_ways_for_subvp()
38 uint32_t total_cache_lines = 0; in dml2_helper_calculate_num_ways_for_subvp()
39 uint32_t bytes_in_mall = 0; in dml2_helper_calculate_num_ways_for_subvp()
40 uint32_t num_mblks = 0; in dml2_helper_calculate_num_ways_for_subvp()
41 uint32_t cache_lines_per_plane = 0; in dml2_helper_calculate_num_ways_for_subvp()
42 uint32_t i = 0; in dml2_helper_calculate_num_ways_for_subvp()
[all …]
/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_timing_generator.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
43 generic_reg_update_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
46 generic_reg_set_soc15(tg110->base.ctx, tg110->offsets.crtc, reg_name, n, __VA_ARGS__)
88 uint32_t field = 0; in dce120_timing_generator_is_in_vertical_blank()
91 tg->ctx, in dce120_timing_generator_is_in_vertical_blank()
93 tg110->offsets.crtc); in dce120_timing_generator_is_in_vertical_blank()
100 /* determine if given timing can be supported by TG */
103 const struct dc_crtc_timing *timing, in dce120_timing_generator_validate_timing() argument
106 uint32_t interlace_factor = timing->flags.INTERLACE ? 2 : 1; in dce120_timing_generator_validate_timing()
108 (timing->v_total - timing->v_addressable - in dce120_timing_generator_validate_timing()
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/linux-6.12.1/drivers/media/i2c/
Dbt819.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * bt819 - BT819A VideoStream Decoder (Rockwell Part)
12 * - moved over to linux>=2.4.x i2c protocol (9/9/2002)
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-ctrls.h>
29 MODULE_DESCRIPTION("Brooktree-819 video decoder driver");
34 module_param(debug, int, 0);
35 MODULE_PARM_DESC(debug, "Debug level (0-1)");
38 /* ----------------------------------------------------------------------- */
57 return &container_of(ctrl->handler, struct bt819, hdl)->sd; in to_sd()
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