Lines Matching +full:timing +full:- +full:0
34 #include <subdev/bios/timing.h>
71 #define T(t) cfg->timing_10_##t
73 nv50_ram_timing_calc(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_calc() argument
75 struct nvbios_ramcfg *cfg = &ram->base.target.bios; in nv50_ram_timing_calc()
76 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv50_ram_timing_calc()
77 struct nvkm_device *device = subdev->device; in nv50_ram_timing_calc()
81 cur2 = nvkm_rd32(device, 0x100228); in nv50_ram_timing_calc()
82 cur4 = nvkm_rd32(device, 0x100230); in nv50_ram_timing_calc()
83 cur7 = nvkm_rd32(device, 0x10023c); in nv50_ram_timing_calc()
84 cur8 = nvkm_rd32(device, 0x100240); in nv50_ram_timing_calc()
86 switch ((!T(CWL)) * ram->base.type) { in nv50_ram_timing_calc()
88 T(CWL) = T(CL) - 1; in nv50_ram_timing_calc()
91 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; in nv50_ram_timing_calc()
96 if (device->chipset == 0xa0) { in nv50_ram_timing_calc()
97 unkt3b = 0x19 + ram->base.next->bios.rammap_00_16_40; in nv50_ram_timing_calc()
98 timing[6] = (0x2d + T(CL) - T(CWL) + in nv50_ram_timing_calc()
99 ram->base.next->bios.rammap_00_16_40) << 16 | in nv50_ram_timing_calc()
101 (0x2f + T(CL) - T(CWL)); in nv50_ram_timing_calc()
103 unkt3b = 0x16; in nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | in nv50_ram_timing_calc()
105 max_t(s8, T(CWL) - 2, 1) << 8 | in nv50_ram_timing_calc()
106 (0x2e + T(CL) - T(CWL)); in nv50_ram_timing_calc()
109 timing[0] = (T(RP) << 24 | T(RAS) << 16 | T(RFC) << 8 | T(RC)); in nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | in nv50_ram_timing_calc()
113 (3 + T(CL) - T(CWL)); in nv50_ram_timing_calc()
114 timing[2] = (T(CWL) - 1) << 24 | in nv50_ram_timing_calc()
118 timing[3] = (unkt3b - 2 + T(CL)) << 24 | in nv50_ram_timing_calc()
120 (T(CL) - 1) << 8 | in nv50_ram_timing_calc()
121 (T(CL) - 1); in nv50_ram_timing_calc()
122 timing[4] = (cur4 & 0xffff0000) | in nv50_ram_timing_calc()
125 timing[5] = T(RFC) << 24 | in nv50_ram_timing_calc()
128 /* Timing 6 is already done above */ in nv50_ram_timing_calc()
129 timing[7] = (cur7 & 0xff00ffff) | (T(CL) - 1) << 16; in nv50_ram_timing_calc()
130 timing[8] = (cur8 & 0xffffff00); in nv50_ram_timing_calc()
133 if (ram->base.type == NVKM_RAM_TYPE_DDR2) { in nv50_ram_timing_calc()
134 timing[5] |= (T(CL) + 3) << 8; in nv50_ram_timing_calc()
135 timing[8] |= (T(CL) - 4); in nv50_ram_timing_calc()
137 if (ram->base.type == NVKM_RAM_TYPE_GDDR3) { in nv50_ram_timing_calc()
138 timing[5] |= (T(CL) + 2) << 8; in nv50_ram_timing_calc()
139 timing[8] |= (T(CL) - 2); in nv50_ram_timing_calc()
143 timing[0], timing[1], timing[2], timing[3]); in nv50_ram_timing_calc()
145 timing[4], timing[5], timing[6], timing[7]); in nv50_ram_timing_calc()
146 nvkm_debug(subdev, " 240: %08x\n", timing[8]); in nv50_ram_timing_calc()
147 return 0; in nv50_ram_timing_calc()
151 nv50_ram_timing_read(struct nv50_ram *ram, u32 *timing) in nv50_ram_timing_read() argument
154 struct nvbios_ramcfg *cfg = &ram->base.target.bios; in nv50_ram_timing_read()
155 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv50_ram_timing_read()
156 struct nvkm_device *device = subdev->device; in nv50_ram_timing_read()
158 for (i = 0; i <= 8; i++) in nv50_ram_timing_read()
159 timing[i] = nvkm_rd32(device, 0x100220 + (i * 4)); in nv50_ram_timing_read()
162 cfg->timing_ver = 0x10; in nv50_ram_timing_read()
163 T(CL) = (timing[3] & 0xff) + 1; in nv50_ram_timing_read()
165 switch (ram->base.type) { in nv50_ram_timing_read()
167 T(CWL) = T(CL) - 1; in nv50_ram_timing_read()
170 T(CWL) = ((timing[2] & 0xff000000) >> 24) + 1; in nv50_ram_timing_read()
173 return -ENOSYS; in nv50_ram_timing_read()
176 T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); in nv50_ram_timing_read()
178 return 0; in nv50_ram_timing_read()
185 ram_mask(hwsq, mr[0], 0x100, 0x100); in nvkm_sddr2_dll_reset()
186 ram_mask(hwsq, mr[0], 0x100, 0x000); in nvkm_sddr2_dll_reset()
193 struct nvkm_gpio *gpio = hwsq->base.subdev->device->gpio; in nv50_ram_gpio()
198 if (nvkm_gpio_get(gpio, 0, tag, DCB_GPIO_UNUSED) != val) { in nv50_ram_gpio()
199 ret = nvkm_gpio_find(gpio, 0, tag, DCB_GPIO_UNUSED, &func); in nv50_ram_gpio()
204 sh = (func.line & 0x7) << 2; in nv50_ram_gpio()
212 ram_mask(hwsq, gpio[reg], (0x3 << sh), ((val | 0x2) << sh)); in nv50_ram_gpio()
221 struct nv50_ramseq *hwsq = &ram->hwsq; in nv50_ram_calc()
222 struct nvkm_subdev *subdev = &ram->base.fb->subdev; in nv50_ram_calc()
223 struct nvkm_bios *bios = subdev->device->bios; in nv50_ram_calc()
232 u32 timing[9]; in nv50_ram_calc() local
234 next = &ram->base.target; in nv50_ram_calc()
235 next->freq = freq; in nv50_ram_calc()
236 ram->base.next = next; in nv50_ram_calc()
239 i = 0; in nv50_ram_calc()
243 if (!data || (ver < 0x25 || ver >= 0x40) || in nv50_ram_calc()
246 return -EINVAL; in nv50_ram_calc()
250 nvbios_rammapEp_from_perf(bios, data, hdr, &next->bios); in nv50_ram_calc()
256 return -EINVAL; in nv50_ram_calc()
260 &next->bios); in nv50_ram_calc()
263 return -EINVAL; in nv50_ram_calc()
267 if (next->bios.ramcfg_timing != 0xff) { in nv50_ram_calc()
268 data = nvbios_timingEp(bios, next->bios.ramcfg_timing, in nv50_ram_calc()
269 &ver, &hdr, &cnt, &len, &next->bios); in nv50_ram_calc()
270 if (!data || ver != 0x10 || hdr < 0x12) { in nv50_ram_calc()
271 nvkm_error(subdev, "invalid/missing timing entry " in nv50_ram_calc()
274 return -EINVAL; in nv50_ram_calc()
276 nv50_ram_timing_calc(ram, timing); in nv50_ram_calc()
278 nv50_ram_timing_read(ram, timing); in nv50_ram_calc()
285 /* Determine ram-specific MR values */ in nv50_ram_calc()
286 ram->base.mr[0] = ram_rd32(hwsq, mr[0]); in nv50_ram_calc()
287 ram->base.mr[1] = ram_rd32(hwsq, mr[1]); in nv50_ram_calc()
288 ram->base.mr[2] = ram_rd32(hwsq, mr[2]); in nv50_ram_calc()
290 switch (ram->base.type) { in nv50_ram_calc()
292 ret = nvkm_gddr3_calc(&ram->base); in nv50_ram_calc()
295 ret = -ENOSYS; in nv50_ram_calc()
304 if (subdev->device->chipset <= 0x96 && !next->bios.ramcfg_00_03_02) in nv50_ram_calc()
305 ram_mask(hwsq, 0x100710, 0x00000200, 0x00000000); in nv50_ram_calc()
308 ram_mask(hwsq, 0x100200, 0x00000800, 0x00000000); in nv50_ram_calc()
311 ram_wr32(hwsq, 0x611200, 0x00003300); in nv50_ram_calc()
312 ram_wr32(hwsq, 0x002504, 0x00000001); /* block fifo */ in nv50_ram_calc()
314 ram_setf(hwsq, 0x10, 0x00); /* disable fb */ in nv50_ram_calc()
315 ram_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */ in nv50_ram_calc()
318 if (next->bios.timing_10_ODT) in nv50_ram_calc()
319 nv50_ram_gpio(hwsq, 0x2e, 1); in nv50_ram_calc()
321 ram_wr32(hwsq, 0x1002d4, 0x00000001); /* precharge */ in nv50_ram_calc()
322 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ in nv50_ram_calc()
323 ram_wr32(hwsq, 0x1002d0, 0x00000001); /* refresh */ in nv50_ram_calc()
324 ram_wr32(hwsq, 0x100210, 0x00000000); /* disable auto-refresh */ in nv50_ram_calc()
325 ram_wr32(hwsq, 0x1002dc, 0x00000001); /* enable self-refresh */ in nv50_ram_calc()
327 ret = nvbios_pll_parse(bios, 0x004008, &mpll); in nv50_ram_calc()
328 mpll.vco2.max_freq = 0; in nv50_ram_calc()
329 if (ret >= 0) { in nv50_ram_calc()
332 if (ret <= 0) in nv50_ram_calc()
333 ret = -EINVAL; in nv50_ram_calc()
336 if (ret < 0) in nv50_ram_calc()
341 r100da0 = 0x00000010; in nv50_ram_calc()
342 r004008 = 0x90000000; in nv50_ram_calc()
344 r100da0 = 0x00000000; in nv50_ram_calc()
345 r004008 = 0x80000000; in nv50_ram_calc()
350 ram_mask(hwsq, 0x00c040, 0xc000c000, 0x0000c000); in nv50_ram_calc()
353 ram_mask(hwsq, 0x004008, 0x00004200, 0x00000200 | in nv50_ram_calc()
354 next->bios.rammap_00_16_40 << 14); in nv50_ram_calc()
355 ram_mask(hwsq, 0x00400c, 0x0000ffff, (N1 << 8) | M1); in nv50_ram_calc()
356 ram_mask(hwsq, 0x004008, 0x91ff0000, r004008); in nv50_ram_calc()
359 if (subdev->device->chipset >= 0x92) in nv50_ram_calc()
360 ram_wr32(hwsq, 0x100da0, r100da0); in nv50_ram_calc()
362 nv50_ram_gpio(hwsq, 0x18, !next->bios.ramcfg_FBVDDQ); in nv50_ram_calc()
366 ram_mask(hwsq, 0x004008, 0x00002200, 0x00002000); in nv50_ram_calc()
368 ram_wr32(hwsq, 0x1002dc, 0x00000000); /* disable self-refresh */ in nv50_ram_calc()
369 ram_wr32(hwsq, 0x1002d4, 0x00000001); /* disable self-refresh */ in nv50_ram_calc()
370 ram_wr32(hwsq, 0x100210, 0x80000000); /* enable auto-refresh */ in nv50_ram_calc()
374 switch (ram->base.type) { in nv50_ram_calc()
376 ram_nuke(hwsq, mr[0]); /* force update */ in nv50_ram_calc()
377 ram_mask(hwsq, mr[0], 0x000, 0x000); in nv50_ram_calc()
381 ram_wr32(hwsq, mr[1], ram->base.mr[1]); in nv50_ram_calc()
382 ram_nuke(hwsq, mr[0]); /* force update */ in nv50_ram_calc()
383 ram_wr32(hwsq, mr[0], ram->base.mr[0]); in nv50_ram_calc()
389 ram_mask(hwsq, timing[3], 0xffffffff, timing[3]); in nv50_ram_calc()
390 ram_mask(hwsq, timing[1], 0xffffffff, timing[1]); in nv50_ram_calc()
391 ram_mask(hwsq, timing[6], 0xffffffff, timing[6]); in nv50_ram_calc()
392 ram_mask(hwsq, timing[7], 0xffffffff, timing[7]); in nv50_ram_calc()
393 ram_mask(hwsq, timing[8], 0xffffffff, timing[8]); in nv50_ram_calc()
394 ram_mask(hwsq, timing[0], 0xffffffff, timing[0]); in nv50_ram_calc()
395 ram_mask(hwsq, timing[2], 0xffffffff, timing[2]); in nv50_ram_calc()
396 ram_mask(hwsq, timing[4], 0xffffffff, timing[4]); in nv50_ram_calc()
397 ram_mask(hwsq, timing[5], 0xffffffff, timing[5]); in nv50_ram_calc()
399 if (!next->bios.ramcfg_00_03_02) in nv50_ram_calc()
400 ram_mask(hwsq, 0x10021c, 0x00010000, 0x00000000); in nv50_ram_calc()
401 ram_mask(hwsq, 0x100200, 0x00001000, !next->bios.ramcfg_00_04_02 << 12); in nv50_ram_calc()
404 unk710 = ram_rd32(hwsq, 0x100710) & ~0x00000100; in nv50_ram_calc()
405 unk714 = ram_rd32(hwsq, 0x100714) & ~0xf0000020; in nv50_ram_calc()
406 unk718 = ram_rd32(hwsq, 0x100718) & ~0x00000100; in nv50_ram_calc()
407 unk71c = ram_rd32(hwsq, 0x10071c) & ~0x00000100; in nv50_ram_calc()
408 if (subdev->device->chipset <= 0x96) { in nv50_ram_calc()
409 unk710 &= ~0x0000006e; in nv50_ram_calc()
410 unk714 &= ~0x00000100; in nv50_ram_calc()
412 if (!next->bios.ramcfg_00_03_08) in nv50_ram_calc()
413 unk710 |= 0x00000060; in nv50_ram_calc()
414 if (!next->bios.ramcfg_FBVDDQ) in nv50_ram_calc()
415 unk714 |= 0x00000100; in nv50_ram_calc()
416 if ( next->bios.ramcfg_00_04_04) in nv50_ram_calc()
417 unk710 |= 0x0000000e; in nv50_ram_calc()
419 unk710 &= ~0x00000001; in nv50_ram_calc()
421 if (!next->bios.ramcfg_00_03_08) in nv50_ram_calc()
422 unk710 |= 0x00000001; in nv50_ram_calc()
425 if ( next->bios.ramcfg_00_03_01) in nv50_ram_calc()
426 unk71c |= 0x00000100; in nv50_ram_calc()
427 if ( next->bios.ramcfg_00_03_02) in nv50_ram_calc()
428 unk710 |= 0x00000100; in nv50_ram_calc()
429 if (!next->bios.ramcfg_00_03_08) in nv50_ram_calc()
430 unk714 |= 0x00000020; in nv50_ram_calc()
431 if ( next->bios.ramcfg_00_04_04) in nv50_ram_calc()
432 unk714 |= 0x70000000; in nv50_ram_calc()
433 if ( next->bios.ramcfg_00_04_20) in nv50_ram_calc()
434 unk718 |= 0x00000100; in nv50_ram_calc()
436 ram_mask(hwsq, 0x100714, 0xffffffff, unk714); in nv50_ram_calc()
437 ram_mask(hwsq, 0x10071c, 0xffffffff, unk71c); in nv50_ram_calc()
438 ram_mask(hwsq, 0x100718, 0xffffffff, unk718); in nv50_ram_calc()
439 ram_mask(hwsq, 0x100710, 0xffffffff, unk710); in nv50_ram_calc()
443 if (next->bios.rammap_00_16_20) { in nv50_ram_calc()
444 ram_wr32(hwsq, 0x1005a0, next->bios.ramcfg_00_07 << 16 | in nv50_ram_calc()
445 next->bios.ramcfg_00_06 << 8 | in nv50_ram_calc()
446 next->bios.ramcfg_00_05); in nv50_ram_calc()
447 ram_wr32(hwsq, 0x1005a4, next->bios.ramcfg_00_09 << 8 | in nv50_ram_calc()
448 next->bios.ramcfg_00_08); in nv50_ram_calc()
449 ram_mask(hwsq, 0x10053c, 0x00001000, 0x00000000); in nv50_ram_calc()
451 ram_mask(hwsq, 0x10053c, 0x00001000, 0x00001000); in nv50_ram_calc()
453 ram_mask(hwsq, mr[1], 0xffffffff, ram->base.mr[1]); in nv50_ram_calc()
455 if (!next->bios.timing_10_ODT) in nv50_ram_calc()
456 nv50_ram_gpio(hwsq, 0x2e, 0); in nv50_ram_calc()
459 if (!next->bios.ramcfg_DLLoff) in nv50_ram_calc()
462 ram_setf(hwsq, 0x10, 0x01); /* enable fb */ in nv50_ram_calc()
463 ram_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */ in nv50_ram_calc()
464 ram_wr32(hwsq, 0x611200, 0x00003330); in nv50_ram_calc()
465 ram_wr32(hwsq, 0x002504, 0x00000000); /* un-block fifo */ in nv50_ram_calc()
467 if (next->bios.rammap_00_17_02) in nv50_ram_calc()
468 ram_mask(hwsq, 0x100200, 0x00000800, 0x00000800); in nv50_ram_calc()
469 if (!next->bios.rammap_00_16_40) in nv50_ram_calc()
470 ram_mask(hwsq, 0x004008, 0x00004000, 0x00000000); in nv50_ram_calc()
471 if (next->bios.ramcfg_00_03_02) in nv50_ram_calc()
472 ram_mask(hwsq, 0x10021c, 0x00010000, 0x00010000); in nv50_ram_calc()
473 if (subdev->device->chipset <= 0x96 && next->bios.ramcfg_00_03_02) in nv50_ram_calc()
474 ram_mask(hwsq, 0x100710, 0x00000200, 0x00000200); in nv50_ram_calc()
476 return 0; in nv50_ram_calc()
483 struct nvkm_device *device = ram->base.fb->subdev.device; in nv50_ram_prog()
484 ram_exec(&ram->hwsq, nvkm_boolopt(device->cfgopt, "NvMemExec", true)); in nv50_ram_prog()
485 return 0; in nv50_ram_prog()
492 ram_exec(&ram->hwsq, false); in nv50_ram_tidy()
505 struct nvkm_subdev *subdev = &ram->fb->subdev; in nv50_fb_vram_rblock()
506 struct nvkm_device *device = subdev->device; in nv50_fb_vram_rblock()
511 r0 = nvkm_rd32(device, 0x100200); in nv50_fb_vram_rblock()
512 r4 = nvkm_rd32(device, 0x100204); in nv50_fb_vram_rblock()
513 rt = nvkm_rd32(device, 0x100250); in nv50_fb_vram_rblock()
515 r0, r4, rt, nvkm_rd32(device, 0x001540)); in nv50_fb_vram_rblock()
517 colbits = (r4 & 0x0000f000) >> 12; in nv50_fb_vram_rblock()
518 rowbitsa = ((r4 & 0x000f0000) >> 16) + 8; in nv50_fb_vram_rblock()
519 rowbitsb = ((r4 & 0x00f00000) >> 20) + 8; in nv50_fb_vram_rblock()
520 banks = 1 << (((r4 & 0x03000000) >> 24) + 2); in nv50_fb_vram_rblock()
522 rowsize = ram->parts * banks * (1 << colbits) * 8; in nv50_fb_vram_rblock()
524 if (r0 & 0x00000004) in nv50_fb_vram_rblock()
527 if (predicted != ram->size) { in nv50_fb_vram_rblock()
529 (u32)(ram->size >> 20)); in nv50_fb_vram_rblock()
544 struct nvkm_device *device = fb->subdev.device; in nv50_ram_ctor()
545 struct nvkm_bios *bios = device->bios; in nv50_ram_ctor()
548 u64 size = nvkm_rd32(device, 0x10020c); in nv50_ram_ctor()
552 switch (nvkm_rd32(device, 0x100714) & 0x00000007) { in nv50_ram_ctor()
553 case 0: type = NVKM_RAM_TYPE_DDR1; break; in nv50_ram_ctor()
567 size = (size & 0x000000ff) << 32 | (size & 0xffffff00); in nv50_ram_ctor()
573 ram->part_mask = (nvkm_rd32(device, 0x001540) & 0x00ff0000) >> 16; in nv50_ram_ctor()
574 ram->parts = hweight8(ram->part_mask); in nv50_ram_ctor()
575 ram->ranks = (nvkm_rd32(device, 0x100200) & 0x4) ? 2 : 1; in nv50_ram_ctor()
576 nvkm_mm_fini(&ram->vram); in nv50_ram_ctor()
578 return nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL, in nv50_ram_ctor()
580 (size - rsvd_head - rsvd_tail) >> NVKM_RAM_MM_SHIFT, in nv50_ram_ctor()
591 return -ENOMEM; in nv50_ram_new()
592 *pram = &ram->base; in nv50_ram_new()
594 ret = nv50_ram_ctor(&nv50_ram_func, fb, &ram->base); in nv50_ram_new()
598 ram->hwsq.r_0x002504 = hwsq_reg(0x002504); in nv50_ram_new()
599 ram->hwsq.r_0x00c040 = hwsq_reg(0x00c040); in nv50_ram_new()
600 ram->hwsq.r_0x004008 = hwsq_reg(0x004008); in nv50_ram_new()
601 ram->hwsq.r_0x00400c = hwsq_reg(0x00400c); in nv50_ram_new()
602 ram->hwsq.r_0x100200 = hwsq_reg(0x100200); in nv50_ram_new()
603 ram->hwsq.r_0x100210 = hwsq_reg(0x100210); in nv50_ram_new()
604 ram->hwsq.r_0x10021c = hwsq_reg(0x10021c); in nv50_ram_new()
605 ram->hwsq.r_0x1002d0 = hwsq_reg(0x1002d0); in nv50_ram_new()
606 ram->hwsq.r_0x1002d4 = hwsq_reg(0x1002d4); in nv50_ram_new()
607 ram->hwsq.r_0x1002dc = hwsq_reg(0x1002dc); in nv50_ram_new()
608 ram->hwsq.r_0x10053c = hwsq_reg(0x10053c); in nv50_ram_new()
609 ram->hwsq.r_0x1005a0 = hwsq_reg(0x1005a0); in nv50_ram_new()
610 ram->hwsq.r_0x1005a4 = hwsq_reg(0x1005a4); in nv50_ram_new()
611 ram->hwsq.r_0x100710 = hwsq_reg(0x100710); in nv50_ram_new()
612 ram->hwsq.r_0x100714 = hwsq_reg(0x100714); in nv50_ram_new()
613 ram->hwsq.r_0x100718 = hwsq_reg(0x100718); in nv50_ram_new()
614 ram->hwsq.r_0x10071c = hwsq_reg(0x10071c); in nv50_ram_new()
615 ram->hwsq.r_0x100da0 = hwsq_stride(0x100da0, 4, ram->base.part_mask); in nv50_ram_new()
616 ram->hwsq.r_0x100e20 = hwsq_reg(0x100e20); in nv50_ram_new()
617 ram->hwsq.r_0x100e24 = hwsq_reg(0x100e24); in nv50_ram_new()
618 ram->hwsq.r_0x611200 = hwsq_reg(0x611200); in nv50_ram_new()
620 for (i = 0; i < 9; i++) in nv50_ram_new()
621 ram->hwsq.r_timing[i] = hwsq_reg(0x100220 + (i * 0x04)); in nv50_ram_new()
623 if (ram->base.ranks > 1) { in nv50_ram_new()
624 ram->hwsq.r_mr[0] = hwsq_reg2(0x1002c0, 0x1002c8); in nv50_ram_new()
625 ram->hwsq.r_mr[1] = hwsq_reg2(0x1002c4, 0x1002cc); in nv50_ram_new()
626 ram->hwsq.r_mr[2] = hwsq_reg2(0x1002e0, 0x1002e8); in nv50_ram_new()
627 ram->hwsq.r_mr[3] = hwsq_reg2(0x1002e4, 0x1002ec); in nv50_ram_new()
629 ram->hwsq.r_mr[0] = hwsq_reg(0x1002c0); in nv50_ram_new()
630 ram->hwsq.r_mr[1] = hwsq_reg(0x1002c4); in nv50_ram_new()
631 ram->hwsq.r_mr[2] = hwsq_reg(0x1002e0); in nv50_ram_new()
632 ram->hwsq.r_mr[3] = hwsq_reg(0x1002e4); in nv50_ram_new()
635 ram->hwsq.r_gpio[0] = hwsq_reg(0x00e104); in nv50_ram_new()
636 ram->hwsq.r_gpio[1] = hwsq_reg(0x00e108); in nv50_ram_new()
637 ram->hwsq.r_gpio[2] = hwsq_reg(0x00e120); in nv50_ram_new()
638 ram->hwsq.r_gpio[3] = hwsq_reg(0x00e124); in nv50_ram_new()
640 return 0; in nv50_ram_new()