| /linux-6.12.1/Documentation/userspace-api/media/v4l/ |
| D | metafmt-pisp-be.rst | 17 The PiSP Back End processes images in tiles, and its configuration requires
30 to be processed and is therefore shared across all the tiles of the image. So
32 across all tiles from the same frame.
40 As the ISP processes images in tiles, each set of tiles parameters describe how
42 parameters consist of 160 bytes of data and to process a batch of tiles several
43 sets of tiles parameters are required.
45 Tiles parameters are passed to the ISP by populating the member of
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| D | pixfmt-yuv-planar.rst | 102 - 64x32 tiles
111 - 16x16 tiles
125 - 4x4 tiles
146 - 4x4 tiles
153 - 16x32 / 16x16 tiles tiled low bits
160 - 16x32 / 16x16 tiles raster low bits
324 pixels in 2D 16x16 tiles, and stores tiles linearly in memory.
329 pixels in 2D 64x32 tiles, and stores 2x2 groups of tiles in
333 If the vertical resolution is an odd number of tiles, the last row of
334 tiles is stored in linear order. The layouts of the luma and chroma
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| /linux-6.12.1/Documentation/devicetree/bindings/arm/ |
| D | arm,integrator.yaml | 14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
15 so the system is modular and can host a variety of CPU tiles called
16 "core tiles" and referred to in the device tree as "core modules".
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| D | arm,vexpress-juno.yaml | 18 The board consist of a motherboard and one or more daughterboards (tiles). The
20 tiles.
130 description: When describing tiles consisting of more than one DCC, its
139 the connection between the motherboard and any tiles. Sometimes the
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| /linux-6.12.1/drivers/gpu/drm/imagination/ |
| D | pvr_rogue_cr_defs_client.h | 103 * must be configured in terms of the number of tiles in X & Y axis.
123 * as the number of tiles defined in the RGX_CR_TE_SCREEN register.
143 * Macrotile width, in tiles. A value of zero corresponds to the maximum size
150 * Macrotile height, in tiles. A value of zero corresponds to the maximum size
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| /linux-6.12.1/include/uapi/drm/ |
| D | drm_fourcc.h | 505 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
522 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
540 * This is a tiled layout using 4Kb tiles in row-major layout.
541 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
561 * considered to be made up of normal 128Bx32 Y tiles, Thus
576 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
587 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
610 * corresponds to an area of 4x1 tiles in the main surface. The main surface
618 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
666 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
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| /linux-6.12.1/drivers/gpu/drm/xe/ |
| D | xe_device.h | 58 return &xe->tiles[0]; in xe_device_get_root_tile()
89 gt = xe->tiles[gt_id].primary_gt; in xe_device_get_gt()
125 for_each_if((tile__) = &(xe__)->tiles[(id__)])
129 for_each_if((tile__) = &(xe__)->tiles[(id__)])
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| D | xe_device_types.h | 121 * at the root tile, and the MSTR_TILE_INTR register will report which tiles
178 * still be accessed by all tiles' GTs.
264 /** @info.tile_count: Number of tiles */
393 /** @tiles: device tiles */
394 struct xe_tile tiles[XE_MAX_TILES_PER_DEVICE]; member
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| D | xe_tile.c | 29 * tiles together in a way such that interrupt notifications from remote tiles
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| D | xe_tile_sysfs_types.h | 17 * When dealing with multiple TILEs, this struct helps to understand which
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| /linux-6.12.1/drivers/video/fbdev/core/ |
| D | Kconfig | 205 where the screen is divided into rectangular sections (tiles), whereas
208 parameters in terms of number of tiles instead of number of pixels.
212 terms of number of tiles in the x- and y-axis.
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| /linux-6.12.1/include/linux/ |
| D | fb.h | 329 __u32 length; /* number of tiles in the map */
337 __u32 width; /* number of tiles in the x-axis */
338 __u32 height; /* number of tiles in the y-axis */
350 __u32 width; /* number of tiles in the x-axis */
351 __u32 height; /* number of tiles in the y-axis */
357 __u32 width; /* number of tiles in the x-axis */
358 __u32 height; /* number of tiles in the y-axis */
361 __u32 length; /* number of tiles to draw */
378 /* all dimensions from hereon are in terms of tiles */
380 /* move a rectangular region of tiles from one area to another*/
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| /linux-6.12.1/Documentation/admin-guide/perf/ |
| D | thunderx2-pmu.rst | 9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
11 to the total number of channels/tiles.
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| /linux-6.12.1/drivers/gpu/drm/xe/display/ |
| D | xe_fb_pin.c | 41 /* The DE ignores the PTEs for the padding tiles */ in write_dpt_rotated()
72 /* The DE ignores the PTEs for the padding tiles */ in write_dpt_remapped()
96 /* display uses 4K tiles instead of bytes here, convert to entries.. */ in __xe_pin_fb_vma_dpt()
179 /* The DE ignores the PTEs for the padding tiles */ in write_ggtt_rotated()
233 /* display seems to use tiles instead of bytes here, so convert it back.. */ in __xe_pin_fb_vma_ggtt()
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| /linux-6.12.1/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| D | nv25.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv25_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv25_fb_tile_comp()
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| D | nv35.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv35_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv35_fb_tile_comp()
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| D | nv36.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv36_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv36_fb_tile_comp()
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| D | nv40.c | 33 u32 tiles = DIV_ROUND_UP(size, 0x80); in nv40_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100); in nv40_fb_tile_comp()
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| D | nv20.c | 46 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv20_fb_tile_comp() local
47 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv20_fb_tile_comp()
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| D | nv30.c | 52 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv30_fb_tile_comp() local
53 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv30_fb_tile_comp()
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| /linux-6.12.1/drivers/media/platform/mediatek/vcodec/decoder/vdec/ |
| D | vdec_vp9_req_lat_if.c | 275 struct vdec_vp9_slice_tiles tiles; member
887 struct vdec_vp9_slice_tiles *tiles; in vdec_vp9_slice_setup_tile() local
897 tiles = &vsi->frame.tiles; in vdec_vp9_slice_setup_tile()
898 tiles->actual_rows = 0; in vdec_vp9_slice_setup_tile()
911 tiles->mi_rows[i] = (offset + 7) >> 3; in vdec_vp9_slice_setup_tile()
912 if (tiles->mi_rows[i]) in vdec_vp9_slice_setup_tile()
913 tiles->actual_rows++; in vdec_vp9_slice_setup_tile()
920 tiles->mi_cols[i] = (offset + 7) >> 3; in vdec_vp9_slice_setup_tile()
1058 * parse tiles according to `6.4 Decode tiles syntax`
1061 * frame contains uncompress header, compressed header and several tiles.
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| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_fb.c | 51 * main surface. And each 64B CCS cache line represents an area of 4x1 Y-tiles
890 unsigned int tiles; in intel_adjust_tile_offset() local
896 tiles = (old_offset - new_offset) / tile_size; in intel_adjust_tile_offset()
898 *y += tiles / pitch_tiles * tile_height; in intel_adjust_tile_offset()
899 *x += tiles % pitch_tiles * tile_width; in intel_adjust_tile_offset()
1001 unsigned int tile_rows, tiles, pitch_tiles; in intel_compute_aligned_offset() local
1016 tiles = *x / tile_width; in intel_compute_aligned_offset()
1019 offset = (tile_rows * pitch_tiles + tiles) * tile_size; in intel_compute_aligned_offset()
1319 * of 8 main surface tiles. in plane_view_dst_stride_tiles()
1512 /* Return number of tiles @color_plane needs. */
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| /linux-6.12.1/drivers/gpu/ipu-v3/ |
| D | ipu-image-convert.c | 27 * of 4*4 or 16 tiles. A conversion is then carried out for each
34 * of tiles as the output frame:
62 * output image. Tiles are numbered row major from top left to bottom
347 "task %u: ctx %p: %s format: %dx%d (%dx%d tiles), %c%c%c%c\n", in dump_format()
403 * Calculate downsizing coefficients, which are the same for all tiles,
406 * Also determine the number of tiles necessary to guarantee that no tile
462 "%s: hscale: >>%u, *8192/%u vscale: >>%u, *8192/%u, %ux%u tiles\n", in calc_image_resize_coefficients()
540 * Output tiles must start at a multiple of 8 bytes horizontally and in find_best_seam()
552 * Tiles in the right row / bottom column may not be allowed to in find_best_seam()
661 * Fill in left position and width and for all tiles in an input column, and
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| /linux-6.12.1/arch/arm/include/debug/ |
| D | vexpress.S | 28 @ - all other (RS1 complaint) tiles use UART mapped
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| /linux-6.12.1/drivers/video/fbdev/ |
| D | gbefb.c | 688 The GBE hardware uses a tiled memory to screen mapping. Tiles are in gbefb_set_par()
691 tiles on the right and/or bottom of the screen if needed. in gbefb_set_par()
709 Tiles have the advantage that they can be allocated individually in in gbefb_set_par()
715 Tiles are still allocated as independent chunks of 64KB of in gbefb_set_par()
750 /* Tell gbe about the tiles table location */ in gbefb_set_par()
1158 printk(KERN_ERR "gbefb: couldn't allocate tiles table\n"); in gbefb_probe()
1192 /* map framebuffer memory into tiles table */ in gbefb_probe()
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