Home
last modified time | relevance | path

Searched +full:tegra210 +full:- +full:timer (Results 1 – 13 of 13) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/timer/
Dnvidia,tegra-timer.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/timer/nvidia,tegra-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra timer
10 - Stephen Warren <swarren@nvidia.com>
13 - if:
17 const: nvidia,tegra210-timer
25 A list of 14 interrupts; one per each timer channels 0 through 13
27 - if:
[all …]
/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
[all …]
Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
[all …]
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]
Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
[all …]
/linux-6.12.1/drivers/clocksource/
Dtimer-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #define pr_fmt(fmt) "tegra-timer: " fmt
24 #include "timer-of.h"
60 * Tegra's timer uses n+1 scheme for the counter, i.e. timer will in tegra_timer_set_next_event()
68 writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV); in tegra_timer_set_next_event()
87 writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1), in tegra_timer_set_periodic()
99 evt->event_handler(evt); in tegra_timer_isr()
139 irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); in tegra_timer_setup()
140 enable_irq(to->clkevt.irq); in tegra_timer_setup()
143 * Tegra's timer uses n+1 scheme for the counter, i.e. timer will in tegra_timer_setup()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/rtc/
Dnvidia,tegra20-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/nvidia,tegra20-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra real-time clock
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 from low-power state.
21 - const: nvidia,tegra20-rtc
22 - items:
[all …]
/linux-6.12.1/drivers/memory/tegra/
Dtegra210-emc-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
559 static void tegra210_emc_train(struct timer_list *timer) in tegra210_emc_train() argument
561 struct tegra210_emc *emc = from_timer(emc, timer, training); in tegra210_emc_train()
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
[all …]
/linux-6.12.1/drivers/clk/tegra/
Dclk-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2012-2020 NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/tegra210-car.h>
18 #include <dt-bindings/reset/tegra210-car.h>
23 #include "clk-id.h"
27 * banks present in the Tegra210 CAR IP block. The banks are
264 * SDM fractional divisor is 16-bit 2's complement signed number within
265 * (-2^12 ... 2^12-1) range. Represented in PLL data structure as unsigned
266 * 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used to
[all …]
Dclk-tegra-periph.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-id.h"
130 #define MASK(x) (BIT(x) - 1)
774 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
787 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
873 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in periph_clk_init()
877 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()
881 data->periph.gate.regs = bank; in periph_clk_init()
899 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in gate_clk_init()
[all …]
/linux-6.12.1/drivers/usb/gadget/udc/
Dtegra-xudc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (c) 2013-2022, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/dma-mapping.h>
246 return (le32_to_cpu(ctx->member) >> (shift)) & (mask); \
253 tmp = le32_to_cpu(ctx->member) & ~((mask) << (shift)); \
255 ctx->member = cpu_to_le32(tmp); \
338 return (le32_to_cpu(trb->member) >> (shift)) & (mask); \
345 tmp = le32_to_cpu(trb->member) & ~((mask) << (shift)); \
347 trb->member = cpu_to_le32(tmp); \
562 return readl(xudc->fpci + offset); in fpci_readl()
[all …]
/linux-6.12.1/drivers/gpu/drm/tegra/
Ddc.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
43 stats->frames = 0; in tegra_dc_stats_reset()
44 stats->vblank = 0; in tegra_dc_stats_reset()
45 stats->underflow = 0; in tegra_dc_stats_reset()
46 stats->overflow = 0; in tegra_dc_stats_reset()
65 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()
66 return plane->offset + offset; in tegra_plane_offset()
70 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()
71 return plane->offset + offset; in tegra_plane_offset()
[all …]
/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
[all …]