Lines Matching +full:tegra210 +full:- +full:timer
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
21 #include "tegra210-emc.h"
22 #include "tegra210-mc.h"
62 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \
69 next->trim_perch_regs[EMC ## chan ## \
559 static void tegra210_emc_train(struct timer_list *timer) in tegra210_emc_train() argument
561 struct tegra210_emc *emc = from_timer(emc, timer, training); in tegra210_emc_train()
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()
570 emc->sequence->periodic_compensation(emc); in tegra210_emc_train()
572 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_train()
574 mod_timer(&emc->training, in tegra210_emc_train()
575 jiffies + msecs_to_jiffies(emc->training_interval)); in tegra210_emc_train()
580 mod_timer(&emc->training, in tegra210_emc_training_start()
581 jiffies + msecs_to_jiffies(emc->training_interval)); in tegra210_emc_training_start()
586 del_timer(&emc->training); in tegra210_emc_training_stop()
595 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_get_temperature()
597 for (i = 0; i < emc->num_devices; i++) { in tegra210_emc_get_temperature()
601 dev_dbg(emc->dev, in tegra210_emc_get_temperature()
610 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_get_temperature()
615 static void tegra210_emc_poll_refresh(struct timer_list *timer) in tegra210_emc_poll_refresh() argument
617 struct tegra210_emc *emc = from_timer(emc, timer, refresh_timer); in tegra210_emc_poll_refresh()
620 if (!emc->debugfs.temperature) in tegra210_emc_poll_refresh()
623 temperature = emc->debugfs.temperature; in tegra210_emc_poll_refresh()
625 if (temperature == emc->temperature) in tegra210_emc_poll_refresh()
631 dev_dbg(emc->dev, "switching to nominal refresh...\n"); in tegra210_emc_poll_refresh()
636 dev_dbg(emc->dev, "switching to 2x refresh...\n"); in tegra210_emc_poll_refresh()
641 dev_dbg(emc->dev, "switching to 4x refresh...\n"); in tegra210_emc_poll_refresh()
646 dev_dbg(emc->dev, "switching to throttle refresh...\n"); in tegra210_emc_poll_refresh()
655 emc->temperature = temperature; in tegra210_emc_poll_refresh()
658 if (atomic_read(&emc->refresh_poll) > 0) { in tegra210_emc_poll_refresh()
659 unsigned int interval = emc->refresh_poll_interval; in tegra210_emc_poll_refresh()
662 mod_timer(&emc->refresh_timer, jiffies + timeout); in tegra210_emc_poll_refresh()
668 atomic_set(&emc->refresh_poll, 0); in tegra210_emc_poll_refresh_stop()
669 del_timer_sync(&emc->refresh_timer); in tegra210_emc_poll_refresh_stop()
674 atomic_set(&emc->refresh_poll, 1); in tegra210_emc_poll_refresh_start()
676 mod_timer(&emc->refresh_timer, in tegra210_emc_poll_refresh_start()
677 jiffies + msecs_to_jiffies(emc->refresh_poll_interval)); in tegra210_emc_poll_refresh_start()
691 struct tegra210_emc *emc = cd->devdata; in tegra210_emc_cd_get_state()
693 *state = atomic_read(&emc->refresh_poll); in tegra210_emc_cd_get_state()
701 struct tegra210_emc *emc = cd->devdata; in tegra210_emc_cd_set_state()
703 if (state == atomic_read(&emc->refresh_poll)) in tegra210_emc_cd_set_state()
722 emc->sequence->set_clock(emc, clksrc); in tegra210_emc_set_clock()
724 if (emc->next->periodic_training) in tegra210_emc_set_clock()
733 u32 dll_setting = emc->next->dll_clk_src; in tegra210_change_dll_src()
760 if (emc->next->clk_out_enb_x_0_clk_enb_emc_dll) in tegra210_change_dll_src()
772 if ((emc->dram_type != DRAM_TYPE_LPDDR2 && in tegra210_emc_set_refresh()
773 emc->dram_type != DRAM_TYPE_LPDDR4) || in tegra210_emc_set_refresh()
774 !emc->last) in tegra210_emc_set_refresh()
775 return -ENODEV; in tegra210_emc_set_refresh()
778 return -EINVAL; in tegra210_emc_set_refresh()
780 if (refresh == emc->refresh) in tegra210_emc_set_refresh()
783 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_set_refresh()
785 if (refresh == TEGRA210_EMC_REFRESH_THROTTLE && emc->derated) in tegra210_emc_set_refresh()
786 timings = emc->derated; in tegra210_emc_set_refresh()
788 timings = emc->nominal; in tegra210_emc_set_refresh()
790 if (timings != emc->timings) { in tegra210_emc_set_refresh()
791 unsigned int index = emc->last - emc->timings; in tegra210_emc_set_refresh()
794 clksrc = emc->provider.configs[index].value | in tegra210_emc_set_refresh()
797 emc->next = &timings[index]; in tegra210_emc_set_refresh()
798 emc->timings = timings; in tegra210_emc_set_refresh()
802 tegra210_emc_adjust_timing(emc, emc->last); in tegra210_emc_set_refresh()
809 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_set_refresh()
824 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_mrr_read()
829 for (i = 0; i < emc->num_channels; i++) { in tegra210_emc_mrr_read()
843 mc_readl(emc->mc, MC_EMEM_ADR_CFG); in tegra210_emc_do_clock_change()
852 dev_warn(emc->dev, "clock change completion error: %d\n", err); in tegra210_emc_do_clock_change()
860 for (i = 0; i < emc->num_timings; i++) in tegra210_emc_find_timing()
861 if (emc->timings[i].rate * 1000UL == rate) in tegra210_emc_find_timing()
862 return &emc->timings[i]; in tegra210_emc_find_timing()
881 return -ETIMEDOUT; in tegra210_emc_wait_for_update()
896 if (next->emc_emrs & 0x1) in tegra210_emc_get_dll_state()
909 for (i = 0; i < emc->num_channels; i++) { in tegra210_emc_timing_update()
916 dev_warn(emc->dev, "timing update error: %d\n", err); in tegra210_emc_timing_update()
941 u32 temp = 0, rate = next->rate / 1000; in tegra210_emc_compensate()
972 delta[0] = 128 * (next->current_dram_clktree[C0D0U0] - in tegra210_emc_compensate()
973 next->trained_dram_clktree[C0D0U0]); in tegra210_emc_compensate()
974 delta[1] = 128 * (next->current_dram_clktree[C0D0U1] - in tegra210_emc_compensate()
975 next->trained_dram_clktree[C0D0U1]); in tegra210_emc_compensate()
976 delta[2] = 128 * (next->current_dram_clktree[C1D0U0] - in tegra210_emc_compensate()
977 next->trained_dram_clktree[C1D0U0]); in tegra210_emc_compensate()
978 delta[3] = 128 * (next->current_dram_clktree[C1D0U1] - in tegra210_emc_compensate()
979 next->trained_dram_clktree[C1D0U1]); in tegra210_emc_compensate()
987 if ((delta_taps[i] > next->tree_margin) || in tegra210_emc_compensate()
988 (delta_taps[i] < (-1 * next->tree_margin))) { in tegra210_emc_compensate()
1010 delta[0] = 128 * (next->current_dram_clktree[C0D1U0] - in tegra210_emc_compensate()
1011 next->trained_dram_clktree[C0D1U0]); in tegra210_emc_compensate()
1012 delta[1] = 128 * (next->current_dram_clktree[C0D1U1] - in tegra210_emc_compensate()
1013 next->trained_dram_clktree[C0D1U1]); in tegra210_emc_compensate()
1014 delta[2] = 128 * (next->current_dram_clktree[C1D1U0] - in tegra210_emc_compensate()
1015 next->trained_dram_clktree[C1D1U0]); in tegra210_emc_compensate()
1016 delta[3] = 128 * (next->current_dram_clktree[C1D1U1] - in tegra210_emc_compensate()
1017 next->trained_dram_clktree[C1D1U1]); in tegra210_emc_compensate()
1025 if ((delta_taps[i] > next->tree_margin) || in tegra210_emc_compensate()
1026 (delta_taps[i] < (-1 * next->tree_margin))) { in tegra210_emc_compensate()
1156 for (i = 0; i < emc->num_channels; i++) in tegra210_emc_dll_prelock()
1161 for (i = 0; i < emc->num_channels; i++) { in tegra210_emc_dll_prelock()
1169 value = emc->next->burst_regs[EMC_DLL_CFG_0_INDEX]; in tegra210_emc_dll_prelock()
1175 if (emc->next->rate >= 400000 && emc->next->rate < 600000) in tegra210_emc_dll_prelock()
1177 else if (emc->next->rate >= 600000 && emc->next->rate < 800000) in tegra210_emc_dll_prelock()
1179 else if (emc->next->rate >= 800000 && emc->next->rate < 1000000) in tegra210_emc_dll_prelock()
1181 else if (emc->next->rate >= 1000000 && emc->next->rate < 1200000) in tegra210_emc_dll_prelock()
1196 for (i = 0; i < emc->num_channels; i++) { in tegra210_emc_dll_prelock()
1228 timing = emc->last; in tegra210_emc_dvfs_power_ramp_up()
1230 timing = emc->next; in tegra210_emc_dvfs_power_ramp_up()
1232 cmd_pad = timing->burst_regs[EMC_PMACRO_CMD_PAD_TX_CTRL_INDEX]; in tegra210_emc_dvfs_power_ramp_up()
1233 dq_pad = timing->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX]; in tegra210_emc_dvfs_power_ramp_up()
1234 rfu1 = timing->burst_regs[EMC_PMACRO_BRICK_CTRL_RFU1_INDEX]; in tegra210_emc_dvfs_power_ramp_up()
1235 cfg5 = timing->burst_regs[EMC_FBIO_CFG5_INDEX]; in tegra210_emc_dvfs_power_ramp_up()
1236 common_tx = timing->burst_regs[EMC_PMACRO_COMMON_PAD_TX_CTRL_INDEX]; in tegra210_emc_dvfs_power_ramp_up()
1344 entry = emc->next; in tegra210_emc_dvfs_power_ramp_down()
1346 entry = emc->last; in tegra210_emc_dvfs_power_ramp_down()
1348 cmd_pad = entry->burst_regs[EMC_PMACRO_CMD_PAD_TX_CTRL_INDEX]; in tegra210_emc_dvfs_power_ramp_down()
1349 dq_pad = entry->burst_regs[EMC_PMACRO_DATA_PAD_TX_CTRL_INDEX]; in tegra210_emc_dvfs_power_ramp_down()
1350 rfu1 = entry->burst_regs[EMC_PMACRO_BRICK_CTRL_RFU1_INDEX]; in tegra210_emc_dvfs_power_ramp_down()
1351 cfg5 = entry->burst_regs[EMC_FBIO_CFG5_INDEX]; in tegra210_emc_dvfs_power_ramp_down()
1352 common_tx = entry->burst_regs[EMC_PMACRO_COMMON_PAD_TX_CTRL_INDEX]; in tegra210_emc_dvfs_power_ramp_down()
1445 timing->current_dram_clktree[C0D0U0] = in tegra210_emc_reset_dram_clktree_values()
1446 timing->trained_dram_clktree[C0D0U0]; in tegra210_emc_reset_dram_clktree_values()
1447 timing->current_dram_clktree[C0D0U1] = in tegra210_emc_reset_dram_clktree_values()
1448 timing->trained_dram_clktree[C0D0U1]; in tegra210_emc_reset_dram_clktree_values()
1449 timing->current_dram_clktree[C1D0U0] = in tegra210_emc_reset_dram_clktree_values()
1450 timing->trained_dram_clktree[C1D0U0]; in tegra210_emc_reset_dram_clktree_values()
1451 timing->current_dram_clktree[C1D0U1] = in tegra210_emc_reset_dram_clktree_values()
1452 timing->trained_dram_clktree[C1D0U1]; in tegra210_emc_reset_dram_clktree_values()
1453 timing->current_dram_clktree[C1D1U0] = in tegra210_emc_reset_dram_clktree_values()
1454 timing->trained_dram_clktree[C1D1U0]; in tegra210_emc_reset_dram_clktree_values()
1455 timing->current_dram_clktree[C1D1U1] = in tegra210_emc_reset_dram_clktree_values()
1456 timing->trained_dram_clktree[C1D1U1]; in tegra210_emc_reset_dram_clktree_values()
1466 for (i = 0; i < emc->num_channels; i++) in update_dll_control()
1495 u32 dsr_cntrl = timing->burst_regs[EMC_DYN_SELF_REF_CONTROL_INDEX]; in tegra210_emc_adjust_timing()
1496 u32 pre_ref = timing->burst_regs[EMC_PRE_REFRESH_REQ_CNT_INDEX]; in tegra210_emc_adjust_timing()
1497 u32 ref = timing->burst_regs[EMC_REFRESH_INDEX]; in tegra210_emc_adjust_timing()
1499 switch (emc->refresh) { in tegra210_emc_adjust_timing()
1517 dev_warn(emc->dev, "failed to set refresh: %d\n", emc->refresh); in tegra210_emc_adjust_timing()
1521 emc_writel(emc, ref, emc->offsets->burst[EMC_REFRESH_INDEX]); in tegra210_emc_adjust_timing()
1523 emc->offsets->burst[EMC_PRE_REFRESH_REQ_CNT_INDEX]); in tegra210_emc_adjust_timing()
1525 emc->offsets->burst[EMC_DYN_SELF_REF_CONTROL_INDEX]); in tegra210_emc_adjust_timing()
1533 unsigned long rate = config->rate; in tegra210_emc_set_rate()
1538 if (rate == emc->last->rate * 1000UL) in tegra210_emc_set_rate()
1541 for (i = 0; i < emc->num_timings; i++) { in tegra210_emc_set_rate()
1542 if (emc->timings[i].rate * 1000UL == rate) { in tegra210_emc_set_rate()
1543 timing = &emc->timings[i]; in tegra210_emc_set_rate()
1549 return -EINVAL; in tegra210_emc_set_rate()
1551 if (rate > 204000000 && !timing->trained) in tegra210_emc_set_rate()
1552 return -EINVAL; in tegra210_emc_set_rate()
1554 emc->next = timing; in tegra210_emc_set_rate()
1555 last_change_delay = ktime_us_delta(ktime_get(), emc->clkchange_time); in tegra210_emc_set_rate()
1557 /* XXX use non-busy-looping sleep? */ in tegra210_emc_set_rate()
1559 (last_change_delay < emc->clkchange_delay)) in tegra210_emc_set_rate()
1560 udelay(emc->clkchange_delay - (int)last_change_delay); in tegra210_emc_set_rate()
1562 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_set_rate()
1563 tegra210_emc_set_clock(emc, config->value); in tegra210_emc_set_rate()
1564 emc->clkchange_time = ktime_get(); in tegra210_emc_set_rate()
1565 emc->last = timing; in tegra210_emc_set_rate()
1566 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_set_rate()
1575 * to control the EMC frequency. The top-level directory can be found here:
1581 * - available_rates: This file contains a list of valid, space-separated
1584 * - min_rate: Writing a value to this file sets the given frequency as the
1589 * - max_rate: Similarily to the min_rate file, writing a value to this file
1601 for (i = 0; i < emc->num_timings; i++) in tegra210_emc_validate_rate()
1602 if (rate == emc->timings[i].rate * 1000UL) in tegra210_emc_validate_rate()
1611 struct tegra210_emc *emc = s->private; in tegra210_emc_debug_available_rates_show()
1615 for (i = 0; i < emc->num_timings; i++) { in tegra210_emc_debug_available_rates_show()
1616 seq_printf(s, "%s%u", prefix, emc->timings[i].rate * 1000); in tegra210_emc_debug_available_rates_show()
1630 *rate = emc->debugfs.min_rate; in tegra210_emc_debug_min_rate_get()
1641 return -EINVAL; in tegra210_emc_debug_min_rate_set()
1643 err = clk_set_min_rate(emc->clk, rate); in tegra210_emc_debug_min_rate_set()
1647 emc->debugfs.min_rate = rate; in tegra210_emc_debug_min_rate_set()
1660 *rate = emc->debugfs.max_rate; in tegra210_emc_debug_max_rate_get()
1671 return -EINVAL; in tegra210_emc_debug_max_rate_set()
1673 err = clk_set_max_rate(emc->clk, rate); in tegra210_emc_debug_max_rate_set()
1677 emc->debugfs.max_rate = rate; in tegra210_emc_debug_max_rate_set()
1691 if (!emc->debugfs.temperature) in tegra210_emc_debug_temperature_get()
1694 value = emc->debugfs.temperature; in tegra210_emc_debug_temperature_get()
1706 return -EINVAL; in tegra210_emc_debug_temperature_set()
1708 emc->debugfs.temperature = temperature; in tegra210_emc_debug_temperature_set()
1719 struct device *dev = emc->dev; in tegra210_emc_debugfs_init()
1723 emc->debugfs.min_rate = ULONG_MAX; in tegra210_emc_debugfs_init()
1724 emc->debugfs.max_rate = 0; in tegra210_emc_debugfs_init()
1726 for (i = 0; i < emc->num_timings; i++) { in tegra210_emc_debugfs_init()
1727 if (emc->timings[i].rate * 1000UL < emc->debugfs.min_rate) in tegra210_emc_debugfs_init()
1728 emc->debugfs.min_rate = emc->timings[i].rate * 1000UL; in tegra210_emc_debugfs_init()
1730 if (emc->timings[i].rate * 1000UL > emc->debugfs.max_rate) in tegra210_emc_debugfs_init()
1731 emc->debugfs.max_rate = emc->timings[i].rate * 1000UL; in tegra210_emc_debugfs_init()
1734 if (!emc->num_timings) { in tegra210_emc_debugfs_init()
1735 emc->debugfs.min_rate = clk_get_rate(emc->clk); in tegra210_emc_debugfs_init()
1736 emc->debugfs.max_rate = emc->debugfs.min_rate; in tegra210_emc_debugfs_init()
1739 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in tegra210_emc_debugfs_init()
1740 emc->debugfs.max_rate); in tegra210_emc_debugfs_init()
1742 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", in tegra210_emc_debugfs_init()
1743 emc->debugfs.min_rate, emc->debugfs.max_rate, in tegra210_emc_debugfs_init()
1744 emc->clk); in tegra210_emc_debugfs_init()
1748 emc->debugfs.root = debugfs_create_dir("emc", NULL); in tegra210_emc_debugfs_init()
1750 debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc, in tegra210_emc_debugfs_init()
1752 debugfs_create_file("min_rate", 0644, emc->debugfs.root, emc, in tegra210_emc_debugfs_init()
1754 debugfs_create_file("max_rate", 0644, emc->debugfs.root, emc, in tegra210_emc_debugfs_init()
1756 debugfs_create_file("temperature", 0644, emc->debugfs.root, emc, in tegra210_emc_debugfs_init()
1765 value = mc_readl(emc->mc, MC_EMEM_ADR_CFG); in tegra210_emc_detect()
1768 emc->num_devices = 2; in tegra210_emc_detect()
1770 emc->num_devices = 1; in tegra210_emc_detect()
1774 emc->dram_type = value & 0x3; in tegra210_emc_detect()
1781 emc->num_channels = 2; in tegra210_emc_detect()
1783 emc->num_channels = 1; in tegra210_emc_detect()
1797 return -EINVAL; in tegra210_emc_validate_timings()
1799 if ((i > 0) && ((rate <= timings[i - 1].rate) || in tegra210_emc_validate_timings()
1800 (min_volt < timings[i - 1].min_volt))) in tegra210_emc_validate_timings()
1801 return -EINVAL; in tegra210_emc_validate_timings()
1819 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra210_emc_probe()
1821 return -ENOMEM; in tegra210_emc_probe()
1823 emc->clk = devm_clk_get(&pdev->dev, "emc"); in tegra210_emc_probe()
1824 if (IS_ERR(emc->clk)) in tegra210_emc_probe()
1825 return PTR_ERR(emc->clk); in tegra210_emc_probe()
1828 spin_lock_init(&emc->lock); in tegra210_emc_probe()
1829 emc->dev = &pdev->dev; in tegra210_emc_probe()
1831 emc->mc = devm_tegra_memory_controller_get(&pdev->dev); in tegra210_emc_probe()
1832 if (IS_ERR(emc->mc)) in tegra210_emc_probe()
1833 return PTR_ERR(emc->mc); in tegra210_emc_probe()
1835 emc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra210_emc_probe()
1836 if (IS_ERR(emc->regs)) in tegra210_emc_probe()
1837 return PTR_ERR(emc->regs); in tegra210_emc_probe()
1840 emc->channel[i] = devm_platform_ioremap_resource(pdev, 1 + i); in tegra210_emc_probe()
1841 if (IS_ERR(emc->channel[i])) in tegra210_emc_probe()
1842 return PTR_ERR(emc->channel[i]); in tegra210_emc_probe()
1847 np = pdev->dev.of_node; in tegra210_emc_probe()
1850 err = of_reserved_mem_device_init_by_name(emc->dev, np, "nominal"); in tegra210_emc_probe()
1852 dev_err(emc->dev, "failed to get nominal EMC table: %d\n", err); in tegra210_emc_probe()
1856 err = of_reserved_mem_device_init_by_name(emc->dev, np, "derated"); in tegra210_emc_probe()
1857 if (err < 0 && err != -ENODEV) { in tegra210_emc_probe()
1858 dev_err(emc->dev, "failed to get derated EMC table: %d\n", err); in tegra210_emc_probe()
1863 if (emc->nominal) { in tegra210_emc_probe()
1864 err = tegra210_emc_validate_timings(emc, emc->nominal, in tegra210_emc_probe()
1865 emc->num_timings); in tegra210_emc_probe()
1870 if (emc->derated) { in tegra210_emc_probe()
1871 err = tegra210_emc_validate_timings(emc, emc->derated, in tegra210_emc_probe()
1872 emc->num_timings); in tegra210_emc_probe()
1878 emc->timings = emc->nominal; in tegra210_emc_probe()
1881 current_rate = clk_get_rate(emc->clk) / 1000; in tegra210_emc_probe()
1883 for (i = 0; i < emc->num_timings; i++) { in tegra210_emc_probe()
1884 if (emc->timings[i].rate == current_rate) { in tegra210_emc_probe()
1885 emc->last = &emc->timings[i]; in tegra210_emc_probe()
1890 if (i == emc->num_timings) { in tegra210_emc_probe()
1891 dev_err(emc->dev, "no EMC table entry found for %lu kHz\n", in tegra210_emc_probe()
1893 err = -ENOENT; in tegra210_emc_probe()
1902 if (emc->timings[0].revision == sequence->revision) { in tegra210_emc_probe()
1903 emc->sequence = sequence; in tegra210_emc_probe()
1908 if (!emc->sequence) { in tegra210_emc_probe()
1909 dev_err(&pdev->dev, "sequence %u not supported\n", in tegra210_emc_probe()
1910 emc->timings[0].revision); in tegra210_emc_probe()
1911 err = -ENOTSUPP; in tegra210_emc_probe()
1915 emc->offsets = &tegra210_emc_table_register_offsets; in tegra210_emc_probe()
1916 emc->refresh = TEGRA210_EMC_REFRESH_NOMINAL; in tegra210_emc_probe()
1918 emc->provider.owner = THIS_MODULE; in tegra210_emc_probe()
1919 emc->provider.dev = &pdev->dev; in tegra210_emc_probe()
1920 emc->provider.set_rate = tegra210_emc_set_rate; in tegra210_emc_probe()
1922 emc->provider.configs = devm_kcalloc(&pdev->dev, emc->num_timings, in tegra210_emc_probe()
1923 sizeof(*emc->provider.configs), in tegra210_emc_probe()
1925 if (!emc->provider.configs) { in tegra210_emc_probe()
1926 err = -ENOMEM; in tegra210_emc_probe()
1930 emc->provider.num_configs = emc->num_timings; in tegra210_emc_probe()
1932 for (i = 0; i < emc->provider.num_configs; i++) { in tegra210_emc_probe()
1933 struct tegra210_emc_timing *timing = &emc->timings[i]; in tegra210_emc_probe()
1935 &emc->provider.configs[i]; in tegra210_emc_probe()
1938 config->rate = timing->rate * 1000UL; in tegra210_emc_probe()
1939 config->value = timing->clk_src_emc; in tegra210_emc_probe()
1941 value = timing->burst_mc_regs[MC_EMEM_ARB_MISC0_INDEX]; in tegra210_emc_probe()
1944 config->same_freq = false; in tegra210_emc_probe()
1946 config->same_freq = true; in tegra210_emc_probe()
1949 err = tegra210_clk_emc_attach(emc->clk, &emc->provider); in tegra210_emc_probe()
1951 dev_err(&pdev->dev, "failed to attach to EMC clock: %d\n", err); in tegra210_emc_probe()
1955 emc->clkchange_delay = 100; in tegra210_emc_probe()
1956 emc->training_interval = 100; in tegra210_emc_probe()
1957 dev_set_drvdata(emc->dev, emc); in tegra210_emc_probe()
1959 timer_setup(&emc->refresh_timer, tegra210_emc_poll_refresh, in tegra210_emc_probe()
1961 atomic_set(&emc->refresh_poll, 0); in tegra210_emc_probe()
1962 emc->refresh_poll_interval = 1000; in tegra210_emc_probe()
1964 timer_setup(&emc->training, tegra210_emc_train, 0); in tegra210_emc_probe()
1968 cd = devm_thermal_of_cooling_device_register(emc->dev, np, "emc", emc, in tegra210_emc_probe()
1972 dev_err(emc->dev, "failed to register cooling device: %d\n", in tegra210_emc_probe()
1980 debugfs_remove_recursive(emc->debugfs.root); in tegra210_emc_probe()
1981 tegra210_clk_emc_detach(emc->clk); in tegra210_emc_probe()
1983 of_reserved_mem_device_release(emc->dev); in tegra210_emc_probe()
1992 debugfs_remove_recursive(emc->debugfs.root); in tegra210_emc_remove()
1993 tegra210_clk_emc_detach(emc->clk); in tegra210_emc_remove()
1994 of_reserved_mem_device_release(emc->dev); in tegra210_emc_remove()
2002 err = clk_rate_exclusive_get(emc->clk); in tegra210_emc_suspend()
2004 dev_err(emc->dev, "failed to acquire clock: %d\n", err); in tegra210_emc_suspend()
2008 emc->resume_rate = clk_get_rate(emc->clk); in tegra210_emc_suspend()
2010 clk_set_rate(emc->clk, 204000000); in tegra210_emc_suspend()
2011 tegra210_clk_emc_detach(emc->clk); in tegra210_emc_suspend()
2013 dev_dbg(dev, "suspending at %lu Hz\n", clk_get_rate(emc->clk)); in tegra210_emc_suspend()
2023 err = tegra210_clk_emc_attach(emc->clk, &emc->provider); in tegra210_emc_resume()
2029 clk_set_rate(emc->clk, emc->resume_rate); in tegra210_emc_resume()
2030 clk_rate_exclusive_put(emc->clk); in tegra210_emc_resume()
2032 dev_dbg(dev, "resuming at %lu Hz\n", clk_get_rate(emc->clk)); in tegra210_emc_resume()
2042 { .compatible = "nvidia,tegra210-emc", },
2049 .name = "tegra210-emc",
2061 MODULE_DESCRIPTION("NVIDIA Tegra210 EMC driver");