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/linux-6.12.1/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra20-dc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^dc@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-dc
21 - nvidia,tegra30-dc
[all …]
Dnvidia,tegra20-host1x.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-host1x.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
13 description: The host1x top-level node defines a number of children, each
19 - enum:
20 - nvidia,tegra20-host1x
21 - nvidia,tegra30-host1x
[all …]
/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra20.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
12 compatible = "nvidia,tegra20";
13 interrupt-parent = <&lic>;
[all …]
Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
[all …]
Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
Dtegra20-medcom-wide.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra20-tamonten.dtsi"
7 model = "Avionic Design Medcom-Wide board";
8 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
15 stdout-path = "serial0:115200n8";
19 dc@54200000 {
35 interrupt-parent = <&gpio>;
38 gpio-controller;
39 #gpio-cells = <2>;
[all …]
Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
[all …]
Dtegra20-colibri-iris.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra20-colibri.dtsi"
9 compatible = "toradex,colibri_t20-iris", "toradex,colibri_t20",
10 "nvidia,tegra20";
22 stdout-path = "serial0:115200n8";
26 dc@54200000 {
35 hdmi-supply = <&reg_5v0>;
41 bl-on {
[all …]
Dtegra20-colibri-eval-v3.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra20-colibri.dtsi"
9 compatible = "toradex,colibri_t20-eval-v3", "toradex,colibri_t20",
10 "nvidia,tegra20";
22 stdout-path = "serial0:115200n8";
26 dc@54200000 {
35 hdmi-supply = <&reg_5v0>;
41 bl-on {
[all …]
Dtegra20-paz00.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
7 #include "tegra20.dtsi"
8 #include "tegra20-cpu-opp.dtsi"
9 #include "tegra20-cpu-opp-microvolt.dtsi"
13 compatible = "compal,paz00", "nvidia,tegra20";
25 stdout-path = "serial0:115200n8";
33 dc@54200000 {
[all …]
Dtegra20-acer-a500-picasso.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20.dtsi"
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
15 compatible = "acer,picasso", "nvidia,tegra20";
[all …]
Dtegra20-asus-tf101.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/atmel-maxtouch.h>
5 #include <dt-bindings/input/gpio-keys.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra20.dtsi"
10 #include "tegra20-cpu-opp.dtsi"
11 #include "tegra20-cpu-opp-microvolt.dtsi"
15 compatible = "asus,tf101", "nvidia,tegra20";
[all …]
Dtegra20-ventana.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/thermal/thermal.h>
6 #include "tegra20.dtsi"
7 #include "tegra20-cpu-opp.dtsi"
8 #include "tegra20-cpu-opp-microvolt.dtsi"
11 model = "NVIDIA Tegra20 Ventana evaluation board";
12 compatible = "nvidia,ventana", "nvidia,tegra20";
21 stdout-path = "serial0:115200n8";
[all …]
Dtegra20-seaboard.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra20.dtsi"
9 compatible = "nvidia,seaboard", "nvidia,tegra20";
18 stdout-path = "serial0:115200n8";
26 dc@54200000 {
37 vdd-supply = <&hdmi_vdd_reg>;
38 pll-supply = <&hdmi_pll_reg>;
39 hdmi-supply = <&vdd_hdmi>;
[all …]
Dtegra20-harmony.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include "tegra20.dtsi"
8 model = "NVIDIA Tegra20 Harmony evaluation board";
9 compatible = "nvidia,harmony", "nvidia,tegra20";
18 stdout-path = "serial0:115200n8";
26 dc@54200000 {
37 hdmi-supply = <&vdd_5v0_hdmi>;
38 vdd-supply = <&hdmi_vdd_reg>;
[all …]
/linux-6.12.1/drivers/gpu/drm/tegra/
Drgb.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include "dc.h"
19 struct tegra_dc *dc; member
81 static void tegra_dc_write_regs(struct tegra_dc *dc, in tegra_dc_write_regs() argument
88 tegra_dc_writel(dc, table[i].value, table[i].offset); in tegra_dc_write_regs()
96 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable)); in tegra_rgb_encoder_disable()
97 tegra_dc_commit(rgb->dc); in tegra_rgb_encoder_disable()
102 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; in tegra_rgb_encoder_enable()
107 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable)); in tegra_rgb_encoder_enable()
110 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS); in tegra_rgb_encoder_enable()
[all …]
Ddrm.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
27 #include <asm/dma-iommu.h>
30 #include "dc.h"
76 struct drm_device *drm = old_state->dev; in tegra_atomic_commit_tail()
77 struct tegra_drm *tegra = drm->dev_private; in tegra_atomic_commit_tail()
79 if (tegra->hub) { in tegra_atomic_commit_tail()
108 return -ENOMEM; in tegra_drm_open()
110 idr_init_base(&fpriv->legacy_contexts, 1); in tegra_drm_open()
111 xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1); in tegra_drm_open()
[all …]
Ddc.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
32 #include "dc.h"
43 stats->frames = 0; in tegra_dc_stats_reset()
44 stats->vblank = 0; in tegra_dc_stats_reset()
45 stats->underflow = 0; in tegra_dc_stats_reset()
46 stats->overflow = 0; in tegra_dc_stats_reset()
50 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) in tegra_dc_readl_active() argument
54 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); in tegra_dc_readl_active()
55 value = tegra_dc_readl(dc, offset); in tegra_dc_readl_active()
[all …]
Dplane.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/dma-mapping.h>
16 #include "dc.h"
33 if (plane->state) in tegra_plane_reset()
34 __drm_atomic_helper_plane_destroy_state(plane->state); in tegra_plane_reset()
36 kfree(plane->state); in tegra_plane_reset()
37 plane->state = NULL; in tegra_plane_reset()
41 plane->state = &state->base; in tegra_plane_reset()
42 plane->state->plane = plane; in tegra_plane_reset()
43 plane->state->zpos = p->index; in tegra_plane_reset()
[all …]
Dhdmi.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <sound/hdmi-codec.h>
37 #include "dc.h"
117 u32 value = readl(hdmi->regs + (offset << 2)); in tegra_hdmi_readl()
119 trace_hdmi_readl(hdmi->dev, offset, value); in tegra_hdmi_readl()
127 trace_hdmi_writel(hdmi->dev, offset, value); in tegra_hdmi_writel()
128 writel(value, hdmi->regs + (offset << 2)); in tegra_hdmi_writel()
376 mutex_lock(&hdmi->audio_lock); in tegra_hdmi_audio_lock()
377 disable_irq(hdmi->irq); in tegra_hdmi_audio_lock()
382 enable_irq(hdmi->irq); in tegra_hdmi_audio_unlock()
[all …]
/linux-6.12.1/drivers/dma/
Dtegra20-apb-dma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * DMA driver for Nvidia's Tegra20 APB DMA controller.
5 * Copyright (c) 2012-2013, NVIDIA CORPORATION. All rights reserved.
12 #include <linux/dma-mapping.h>
103 * on-flight burst and update DMA status register.
144 * sub-transfer as per requester details and hw support.
201 /* Channel-slave specific configuration */
232 writel(val, tdma->base_addr + reg); in tdma_write()
238 writel(val, tdc->chan_addr + reg); in tdc_write()
243 return readl(tdc->chan_addr + reg); in tdc_read()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
[all …]
Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
[all …]
Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
[all …]
Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
[all …]

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