Lines Matching +full:tegra20 +full:- +full:dc
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/dma-mapping.h>
16 #include "dc.h"
33 if (plane->state) in tegra_plane_reset()
34 __drm_atomic_helper_plane_destroy_state(plane->state); in tegra_plane_reset()
36 kfree(plane->state); in tegra_plane_reset()
37 plane->state = NULL; in tegra_plane_reset()
41 plane->state = &state->base; in tegra_plane_reset()
42 plane->state->plane = plane; in tegra_plane_reset()
43 plane->state->zpos = p->index; in tegra_plane_reset()
44 plane->state->normalized_zpos = p->index; in tegra_plane_reset()
47 state->iova[i] = DMA_MAPPING_ERROR; in tegra_plane_reset()
54 struct tegra_plane_state *state = to_tegra_plane_state(plane->state); in tegra_plane_atomic_duplicate_state()
62 __drm_atomic_helper_plane_duplicate_state(plane, ©->base); in tegra_plane_atomic_duplicate_state()
63 copy->tiling = state->tiling; in tegra_plane_atomic_duplicate_state()
64 copy->format = state->format; in tegra_plane_atomic_duplicate_state()
65 copy->swap = state->swap; in tegra_plane_atomic_duplicate_state()
66 copy->reflect_x = state->reflect_x; in tegra_plane_atomic_duplicate_state()
67 copy->reflect_y = state->reflect_y; in tegra_plane_atomic_duplicate_state()
68 copy->opaque = state->opaque; in tegra_plane_atomic_duplicate_state()
69 copy->total_peak_memory_bandwidth = state->total_peak_memory_bandwidth; in tegra_plane_atomic_duplicate_state()
70 copy->peak_memory_bandwidth = state->peak_memory_bandwidth; in tegra_plane_atomic_duplicate_state()
71 copy->avg_memory_bandwidth = state->avg_memory_bandwidth; in tegra_plane_atomic_duplicate_state()
74 copy->blending[i] = state->blending[i]; in tegra_plane_atomic_duplicate_state()
77 copy->iova[i] = DMA_MAPPING_ERROR; in tegra_plane_atomic_duplicate_state()
78 copy->map[i] = NULL; in tegra_plane_atomic_duplicate_state()
81 return ©->base; in tegra_plane_atomic_duplicate_state()
95 drm_for_each_crtc(crtc, plane->dev) { in tegra_plane_supports_sector_layout()
96 if (plane->possible_crtcs & drm_crtc_mask(crtc)) { in tegra_plane_supports_sector_layout()
97 struct tegra_dc *dc = to_tegra_dc(crtc); in tegra_plane_supports_sector_layout() local
99 if (!dc->soc->supports_sector_layout) in tegra_plane_supports_sector_layout()
124 if (info->num_planes == 1) in tegra_plane_format_mod_supported()
140 static int tegra_dc_pin(struct tegra_dc *dc, struct tegra_plane_state *state) in tegra_dc_pin() argument
145 for (i = 0; i < state->base.fb->format->num_planes; i++) { in tegra_dc_pin()
146 struct tegra_bo *bo = tegra_fb_get_plane(state->base.fb, i); in tegra_dc_pin()
149 map = host1x_bo_pin(dc->dev, &bo->base, DMA_TO_DEVICE, &dc->client.cache); in tegra_dc_pin()
155 if (!dc->client.group) { in tegra_dc_pin()
162 if (map->chunks > 1) { in tegra_dc_pin()
163 err = -EINVAL; in tegra_dc_pin()
167 state->iova[i] = map->phys; in tegra_dc_pin()
169 state->iova[i] = bo->iova; in tegra_dc_pin()
172 state->map[i] = map; in tegra_dc_pin()
178 dev_err(dc->dev, "failed to map plane %u: %d\n", i, err); in tegra_dc_pin()
180 while (i--) { in tegra_dc_pin()
181 host1x_bo_unpin(state->map[i]); in tegra_dc_pin()
182 state->iova[i] = DMA_MAPPING_ERROR; in tegra_dc_pin()
183 state->map[i] = NULL; in tegra_dc_pin()
189 static void tegra_dc_unpin(struct tegra_dc *dc, struct tegra_plane_state *state) in tegra_dc_unpin() argument
193 for (i = 0; i < state->base.fb->format->num_planes; i++) { in tegra_dc_unpin()
194 host1x_bo_unpin(state->map[i]); in tegra_dc_unpin()
195 state->iova[i] = DMA_MAPPING_ERROR; in tegra_dc_unpin()
196 state->map[i] = NULL; in tegra_dc_unpin()
203 struct tegra_dc *dc = to_tegra_dc(state->crtc); in tegra_plane_prepare_fb() local
206 if (!state->fb) in tegra_plane_prepare_fb()
213 return tegra_dc_pin(dc, to_tegra_plane_state(state)); in tegra_plane_prepare_fb()
219 struct tegra_dc *dc = to_tegra_dc(state->crtc); in tegra_plane_cleanup_fb() local
221 if (dc) in tegra_plane_cleanup_fb()
222 tegra_dc_unpin(dc, to_tegra_plane_state(state)); in tegra_plane_cleanup_fb()
234 if (!state->visible) in tegra_plane_calculate_memory_bandwidth()
237 crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); in tegra_plane_calculate_memory_bandwidth()
239 return -EINVAL; in tegra_plane_calculate_memory_bandwidth()
241 src_w = drm_rect_width(&state->src) >> 16; in tegra_plane_calculate_memory_bandwidth()
242 src_h = drm_rect_height(&state->src) >> 16; in tegra_plane_calculate_memory_bandwidth()
243 dst_w = drm_rect_width(&state->dst); in tegra_plane_calculate_memory_bandwidth()
244 dst_h = drm_rect_height(&state->dst); in tegra_plane_calculate_memory_bandwidth()
246 fmt = state->fb->format; in tegra_plane_calculate_memory_bandwidth()
247 soc = to_tegra_dc(state->crtc)->soc; in tegra_plane_calculate_memory_bandwidth()
255 for (i = 0, bpp = 0; i < fmt->num_planes; i++) { in tegra_plane_calculate_memory_bandwidth()
256 unsigned int bpp_plane = fmt->cpp[i] * 8; in tegra_plane_calculate_memory_bandwidth()
259 * Sub-sampling is relevant for chroma planes only and vertical in tegra_plane_calculate_memory_bandwidth()
260 * readouts are not cached, hence only horizontal sub-sampling in tegra_plane_calculate_memory_bandwidth()
264 bpp_plane /= fmt->hsub; in tegra_plane_calculate_memory_bandwidth()
271 avg_bandwidth *= drm_mode_vrefresh(&crtc_state->adjusted_mode); in tegra_plane_calculate_memory_bandwidth()
276 peak_bandwidth = DIV_ROUND_UP(crtc_state->adjusted_mode.clock * bpp, 8); in tegra_plane_calculate_memory_bandwidth()
279 * Tegra30/114 Memory Controller can't interleave DC memory requests in tegra_plane_calculate_memory_bandwidth()
280 * for the tiled windows because DC uses 16-bytes atom, while DDR3 in tegra_plane_calculate_memory_bandwidth()
281 * uses 32-bytes atom. Hence there is x2 memory overfetch for tiled in tegra_plane_calculate_memory_bandwidth()
284 if (soc->plane_tiled_memory_bandwidth_x2 && in tegra_plane_calculate_memory_bandwidth()
285 tegra_state->tiling.mode == TEGRA_BO_TILING_MODE_TILED) in tegra_plane_calculate_memory_bandwidth()
291 tegra_state->peak_memory_bandwidth = kBps_to_icc(peak_bandwidth) * mul; in tegra_plane_calculate_memory_bandwidth()
292 tegra_state->avg_memory_bandwidth = kBps_to_icc(avg_bandwidth) * mul; in tegra_plane_calculate_memory_bandwidth()
305 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); in tegra_plane_state_add()
321 tegra->planes |= WIN_A_ACT_REQ << plane->index; in tegra_plane_state_add()
411 return -EINVAL; in tegra_plane_format()
419 return -EINVAL; in tegra_plane_format()
427 return -EINVAL; in tegra_plane_format()
470 return -EINVAL; in tegra_plane_format()
583 return -EINVAL; in tegra_plane_format_get_alpha()
587 * This is applicable to Tegra20 and Tegra30 only where the opaque formats can
596 switch (state->format) { in tegra_plane_setup_opacity()
601 state->opaque = false; in tegra_plane_setup_opacity()
605 err = tegra_plane_format_get_alpha(state->format, &format); in tegra_plane_setup_opacity()
609 state->format = format; in tegra_plane_setup_opacity()
610 state->opaque = true; in tegra_plane_setup_opacity()
623 old = drm_atomic_get_old_plane_state(state->base.state, &tegra->base); in tegra_plane_check_transparency()
626 if (old->normalized_zpos == state->base.normalized_zpos && in tegra_plane_check_transparency()
627 to_tegra_plane_state(old)->opaque == state->opaque) in tegra_plane_check_transparency()
631 drm_for_each_plane(plane, tegra->base.dev) { in tegra_plane_check_transparency()
635 if (p == tegra || p->dc != tegra->dc) in tegra_plane_check_transparency()
638 plane_state = drm_atomic_get_plane_state(state->base.state, in tegra_plane_check_transparency()
655 if (i == plane->index) in tegra_plane_get_overlap_index()
658 if (i == other->index) in tegra_plane_get_overlap_index()
674 for_each_new_plane_in_state(state->base.state, plane, new, i) { in tegra_plane_update_transparency()
679 if (p == tegra || p->dc != tegra->dc) in tegra_plane_update_transparency()
684 if (new->fb && __drm_format_has_alpha(new->fb->format->format)) in tegra_plane_update_transparency()
685 state->blending[index].alpha = true; in tegra_plane_update_transparency()
687 state->blending[index].alpha = false; in tegra_plane_update_transparency()
689 if (new->normalized_zpos > state->base.normalized_zpos) in tegra_plane_update_transparency()
690 state->blending[index].top = true; in tegra_plane_update_transparency()
692 state->blending[index].top = false; in tegra_plane_update_transparency()
700 if (!new->fb) in tegra_plane_update_transparency()
701 state->blending[index].top = (index == 1); in tegra_plane_update_transparency()
726 drm_for_each_plane(plane, tegra->base.dev) { in tegra_plane_setup_transparency()
730 if (p->dc != tegra->dc) in tegra_plane_setup_transparency()
733 new = drm_atomic_get_new_plane_state(state->base.state, plane); in tegra_plane_setup_transparency()
740 if (new->fb) in tegra_plane_setup_transparency()
769 const char *icc_name = tegra_plane_icc_names[plane->index]; in tegra_plane_interconnect_init()
770 struct device *dev = plane->dc->dev; in tegra_plane_interconnect_init()
771 struct tegra_dc *dc = plane->dc; in tegra_plane_interconnect_init() local
774 if (WARN_ON(plane->index >= TEGRA_DC_LEGACY_PLANES_NUM) || in tegra_plane_interconnect_init()
775 WARN_ON(!tegra_plane_icc_names[plane->index])) in tegra_plane_interconnect_init()
776 return -EINVAL; in tegra_plane_interconnect_init()
778 plane->icc_mem = devm_of_icc_get(dev, icc_name); in tegra_plane_interconnect_init()
779 err = PTR_ERR_OR_ZERO(plane->icc_mem); in tegra_plane_interconnect_init()
784 /* plane B on T20/30 has a dedicated memory client for a 6-tap vertical filter */ in tegra_plane_interconnect_init()
785 if (plane->index == 1 && dc->soc->has_win_b_vfilter_mem_client) { in tegra_plane_interconnect_init()
786 plane->icc_mem_vfilter = devm_of_icc_get(dev, "winb-vfilter"); in tegra_plane_interconnect_init()
787 err = PTR_ERR_OR_ZERO(plane->icc_mem_vfilter); in tegra_plane_interconnect_init()
790 "winb-vfilter"); in tegra_plane_interconnect_init()