/linux-6.12.1/drivers/cpufreq/ |
D | sa1110-cpufreq.c | 39 u_char twr; /* write recovery time (ns) */ member 56 .twr = 10, 65 .twr = 8, 74 .twr = 9, 82 .twr = 10, 91 .twr = 16, /* Trdl: 2 CLKs */ 100 .twr = 8, 109 .twr = 8, 146 u_int mem_khz, sd_khz, trp, twr; in sdram_calculate_timing() local 164 twr = ns_to_cycles(sdram->twr, mem_khz); in sdram_calculate_timing() [all …]
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/linux-6.12.1/drivers/memory/ |
D | jedec_ddr_data.c | 39 .tWR = 15000, 60 .tWR = 15000, 81 .tWR = 15000, 102 .tWR = 15000, 123 .tWR = 3,
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D | of_memory.c | 40 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_get_min_tck() 72 ret |= of_property_read_u32(np, "tWR", &tim->tWR); in of_do_get_timings() 183 ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR); in of_lpddr3_get_min_tck() 229 ret |= of_property_read_u32(np, "tWR", &tim->tWR); in of_lpddr3_do_get_timings()
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D | jedec_ddr.h | 152 u32 tWR; member 176 u32 tWR; member 236 u32 tWR; member 265 u32 tWR; member
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/linux-6.12.1/arch/powerpc/platforms/85xx/ |
D | twr_p102x.c | 8 * TWR-P102x Board Setup 102 pr_info("TWR-P1025 board from Freescale Semiconductor\n"); in twr_p1025_setup_arch() 108 .name = "TWR-P1025", in define_machine() 109 .compatible = "fsl,TWR-P1025", in define_machine()
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D | Kconfig | 144 bool "Freescale TWR-P102x" 147 This option enables support for the TWR-P1025 board.
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/linux-6.12.1/arch/arm/boot/dts/ti/omap/ |
D | elpida_ecb240abacn.dtsi | 14 tWR-min-tck = <3>; 30 tWR = <15000>; 52 tWR = <15000>;
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/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/ddr/ |
D | jedec,lpddr2.yaml | 98 tWR-min-tck: 153 tWR-min-tck = <3>; 169 tWR = <15000>; 190 tWR = <15000>;
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D | jedec,lpddr3.yaml | 149 tWR-min-tck: 215 tWR-min-tck = <7>; 238 tWR = <7500>;
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D | jedec,lpddr2-timings.yaml | 77 tWR: 129 tWR = <15000>;
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D | jedec,lpddr3-timings.yaml | 104 tWR: 152 tWR = <7500>;
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/linux-6.12.1/arch/powerpc/boot/dts/fsl/ |
D | p1025twr.dts | 2 * P1025 TWR Device Tree Source (32-bit address map) 38 compatible = "fsl,TWR-P1025";
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D | p1025twr.dtsi | 2 * P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
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/linux-6.12.1/arch/arm/boot/dts/nxp/ls/ |
D | ls1021a-twr.dts | 11 model = "LS1021A TWR Board"; 12 compatible = "fsl,ls1021a-twr", "fsl,ls1021a";
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D | Makefile | 8 ls1021a-twr.dtb
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/linux-6.12.1/arch/arm/boot/dts/nxp/vf/ |
D | Makefile | 9 vf610-twr.dtb \
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D | vf610-twr.dts | 10 compatible = "fsl,vf610-twr", "fsl,vf610"; 169 vf610-twr {
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D | vf610-zii-ssmb-dtu.dts | 11 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
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D | vf610-zii-ssmb-spu3.dts | 11 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
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D | vf610-zii-dev.dtsi | 4 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
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/linux-6.12.1/drivers/gpu/drm/amd/amdgpu/ |
D | amdgpu_eeprom.c | 157 * self-writing cycle, tWR (tW), is 10 ms. in __amdgpu_eeprom_xfer() 162 * usually smaller than tWR (tW). in __amdgpu_eeprom_xfer()
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/linux-6.12.1/drivers/memory/samsung/ |
D | exynos5422-dmc.c | 218 TIMING_FIELD("tWR", 24, 27), 1095 val = dmc->timings->tWR / clk_period_ps; in create_timings_aligned() 1096 val += dmc->timings->tWR % clk_period_ps ? 1 : 0; in create_timings_aligned() 1097 val = max(val, dmc->min_tck->tWR); in create_timings_aligned()
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/linux-6.12.1/arch/arm/boot/dts/samsung/ |
D | exynos5422-odroid-core.dtsi | 349 tWR-min-tck = <7>; 375 tWR = <7500>;
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/linux-6.12.1/drivers/video/fbdev/aty/ |
D | aty128fb.c | 324 u8 Twr; member 339 .Twr = 1, 353 .Twr = 1, 367 .Twr = 2, 1444 m->Twr + in aty128_ddafifo()
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/linux-6.12.1/arch/mips/include/asm/octeon/ |
D | cvmx-lmcx-defs.h | 1289 uint64_t twr:3; member 1313 uint64_t twr:3; 1330 uint64_t twr:3; member 1354 uint64_t twr:3;
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