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/linux-6.12.1/drivers/media/i2c/
Dccs-pll.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
22 /* op pix clock is for all lanes in total normally */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
43 * @pll_ip_clk_freq_hz: PLL input clock frequency
44 * @pll_op_clk_freq_hz: PLL output clock frequency
54 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
[all …]
/linux-6.12.1/Documentation/timers/
Dtimekeeping.rst2 Clock sources, Clock events, sched_clock() and delay timers
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
25 The purpose of the clock source is to provide a timeline for the system that
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/linux-6.12.1/Documentation/virt/hyperv/
Dclocks.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -----
8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
12 architectural system counter is functional in guest VMs on Hyper-V.
13 While Hyper-V also provides a synthetic system clock and four synthetic
14 per-CPU timers as described in the TLFS, they are not used by the
15 Linux kernel in a Hyper-V guest on arm64. However, older versions
16 of Hyper-V for arm64 only partially virtualize the ARMv8
19 Linux kernel versions on these older Hyper-V versions requires an
20 out-of-tree patch to use the Hyper-V synthetic clocks/timers instead.
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/linux-6.12.1/arch/sparc/include/asm/
Dbbc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * bbc.h: Defines for BootBus Controller found on UltraSPARC-III
12 /* Register sizes are indicated by "B" (Byte, 1-byte),
13 * "H" (Half-word, 2 bytes), "W" (Word, 4 bytes) or
26 #define BBC_CSC 0x0d /* [B] Clock Synthesizers Control*/
29 #define BBC_ES_DACT 0x14 /* [B] E* De-Assert Change Time */
30 #define BBC_ES_DABT 0x15 /* [B] E* De-Assert Bypass Time */
33 #define BBC_ES_FSL 0x1c /* [W] E* Frequency Switch Latency*/
38 #define BBC_I2C_0_S1 0x2e /* [B] I2C ctrlr-0 reg S1 */
39 #define BBC_I2C_0_S0 0x2f /* [B] I2C ctrlr-0 regs S0,S0',S2,S3*/
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/linux-6.12.1/Documentation/driver-api/media/
Dcamera-sensor.rst1 .. SPDX-License-Identifier: GPL-2.0
8 This document covers the in-kernel APIs only. For the best practices on
12 CSI-2, parallel and BT.656 buses
13 --------------------------------
15 Please see :ref:`transmitter-receiver`.
18 ---------------
20 Camera sensors have an internal clock tree including a PLL and a number of
21 divisors. The clock tree is generally configured by the driver based on a few
22 input parameters that are specific to the hardware: the external clock frequency
23 and the link frequency. The two parameters generally are obtained from system
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/linux-6.12.1/arch/powerpc/include/asm/
Dmpc5121.h1 /* SPDX-License-Identifier: GPL-2.0-only */
23 * Clock Control Module
26 u32 spmr; /* System PLL Mode Register */
27 u32 sccr1; /* System Clock Control Register 1 */
28 u32 sccr2; /* System Clock Control Register 2 */
29 u32 scfr1; /* System Clock Frequency Register 1 */
30 u32 scfr2; /* System Clock Frequency Register 2 */
31 u32 scfr2s; /* System Clock Frequency Shadow Register 2 */
33 u32 psc_ccr[12]; /* PSC Clock Control Registers */
34 u32 spccr; /* SPDIF Clock Control Register */
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/linux-6.12.1/drivers/net/ethernet/intel/e1000e/
Dptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
4 /* PTP 1588 Hardware Clock (PHC)
5 * Derived from PTP Hardware Clock driver for Intel 82576 and 82580 (igb)
18 * e1000e_phc_adjfine - adjust the frequency of the hardware clock
19 * @ptp: ptp clock structure
20 * @delta: Desired frequency chance in scaled parts per million
22 * Adjust the frequency of the PHC cycle counter by the indicated delta from
23 * the base frequency.
31 struct e1000_hw *hw = &adapter->hw; in e1000e_phc_adjfine()
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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dnvidia,tegra124-car.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/nvidia,tegra124-car.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Clock and Reset Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The Clock and Reset (CAR) is the HW module responsible for muxing and gating
18 the clock source programming and most of the clock dividers.
20 CLKGEN input signals include the external clock for the reference frequency
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Dlpc1850-cgu.txt1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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Drenesas,emev2-smu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas EMMA Mobile EV2 System Management Unit
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
15 This is not a clock provider, but clocks under SMU depend on it.
19 const: renesas,emev2-smu
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/linux-6.12.1/include/linux/
Dptp_clock_kernel.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * PTP 1588 clock support
19 * struct ptp_clock_request - request PTP clock event
47 * struct ptp_system_timestamp - system time corresponding to a PHC timestamp
48 * @pre_ts: system timestamp before capturing PHC
49 * @post_ts: system timestamp after capturing PHC
50 * @clockid: clock-base used for capturing the system timestamps
59 * struct ptp_clock_info - describes a PTP hardware clock
61 * @owner: The clock driver should set to THIS_MODULE.
62 * @name: A short "friendly name" to identify the clock and to
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/linux-6.12.1/Documentation/devicetree/bindings/ptp/
Dfsl,ptp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dsimple-card.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
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Daudio-graph-port.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/audio-graph-port.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
15 port-base:
17 - $ref: /schemas/graph.yaml#/$defs/port-base
18 - $ref: /schemas/sound/dai-params.yaml#
20 mclk-fs:
21 $ref: simple-card.yaml#/definitions/mclk-fs
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
18 clock from a group of clients. Typically, a system has a single Arbitration
20 Arbitration Domains to increase the effective system bandwidth.
22 Protocol Arbiter, which manage a related pool of memory devices. A system
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/linux-6.12.1/Documentation/devicetree/bindings/timer/
Dbrcm,bcm2835-system-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/brcm,bcm2835-system-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: BCM2835 System Timer
10 - Stefan Wahren <wahrenst@gmx.net>
11 - Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
14 The System Timer peripheral provides four 32-bit timer channels and a
15 single 64-bit free running counter. Each channel has an output compare
21 const: brcm,bcm2835-system-timer
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Darm,armv7m-systick.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/arm,armv7m-systick.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARMv7M System Timer
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
13 description: ARMv7-M includes a system timer, known as SysTick.
17 const: arm,armv7m-systick
25 clock-frequency: true
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/linux-6.12.1/arch/arm64/boot/dts/broadcom/
Dbcm2712.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <2>;
8 #size-cells = <2>;
10 interrupt-parent = <&gicv2>;
13 /* The oscillator is the root of the clock tree. */
14 clk_osc: clk-osc {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-output-names = "osc";
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/linux-6.12.1/Documentation/ABI/testing/
Dsysfs-devices-system-cpu1 What: /sys/devices/system/cpu/
2 Date: pre-git history
3 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
10 /sys/devices/system/cpu/cpuX/
12 What: /sys/devices/system/cpu/kernel_max
13 /sys/devices/system/cpu/offline
14 /sys/devices/system/cpu/online
15 /sys/devices/system/cpu/possible
16 /sys/devices/system/cpu/present
18 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org>
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/i2c/
Dst,nomadik-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,nomadik-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 STn8815. It was part of the prototype STn8500 which then became ST-Ericsson
15 - Linus Walleij <linus.walleij@linaro.org>
23 - st,nomadik-i2c
24 - mobileye,eyeq5-i2c
26 - compatible
31 - items:
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Di2c-img-scb.txt4 - compatible: "img,scb-i2c"
5 - reg: Physical base address and length of controller registers
6 - interrupts: Interrupt number used by the controller
7 - clocks : Should contain a clock specifier for each entry in clock-names
8 - clock-names : Should contain the following entries:
9 "scb", for the SCB core clock.
10 "sys", for the system clock.
11 - clock-frequency: The I2C bus frequency in Hz
12 - #address-cells: Should be <1>
13 - #size-cells: Should be <0>
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/linux-6.12.1/Documentation/devicetree/bindings/mfd/
Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of
17 platform. Audio system topology, clocking and power can all be
25 [2] include/dt-bindings/pinctrl/lochnagar.h
26 [3] include/dt-bindings/clock/lochnagar.h
28 And these documents for the required sub-node binding details:
29 [4] Clock: ../clock/cirrus,lochnagar.yaml
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/linux-6.12.1/tools/power/x86/turbostat/
Dturbostat.83 turbostat \- Report processor frequency and idle statistics
12 .RB [ "\--interval seconds" ]
14 \fBturbostat \fP reports processor topology, frequency,
15 idle power-state statistics, temperature and power on X86 processors.
19 in one-shot upon its completion.
22 The 5-second interval can be changed using the --interval option.
26 Options can be specified with a single or double '-', and only as much of the option
27 name as necessary to disambiguate it from others is necessary. Note that options are case-sensitiv…
29 \fB--add attributes\fP add column with counter having specified 'attributes'. The 'location' attri…
36 … event for given device from /sys/bus/event_source/devices/<device>/events/<event> eg. c1-residency
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dti,cc1352p7.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 - Ayush Singh <ayushdevel1325@gmail.com>
21 - description: high-frequency main system (MCU and peripherals) clock
22 - description: low-frequency system clock
24 clock-names:
26 - const: sclk_hf
27 - const: sclk_lf
29 reset-gpios:
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/linux-6.12.1/arch/arm/boot/dts/samsung/
Ds5pv210-smdkc110.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2013-2014 Samsung Electronics, Co. Ltd.
10 * Board device tree source for YIC System SMDC110 board.
12 * NOTE: This file is completely based on original board file for mach-smdkc110
17 /dts-v1/;
18 #include <dt-bindings/input/input.h>
22 model = "YIC System SMDKC110 based on S5PC110";
34 pmic_ap_clk: clock-0 {
35 /* Workaround for missing PMIC and its clock */
36 compatible = "fixed-clock";
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