Lines Matching +full:system +full:- +full:clock +full:- +full:frequency

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas EMMA Mobile EV2 System Management Unit
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
15 This is not a clock provider, but clocks under SMU depend on it.
19 const: renesas,emev2-smu
24 '#address-cells':
27 '#size-cells':
31 - compatible
32 - reg
33 - '#address-cells'
34 - '#size-cells'
42 "Serial clock generator" in fig. "Clock System Overview" of the manual,
43 and "xxx frequency division setting register" (XXXCLKDIV) registers.
44 This makes internal (neither input nor output) clock that is provided
49 const: renesas,emev2-smu-clkdiv
60 '#clock-cells':
64 - compatible
65 - reg
66 - clocks
67 - '#clock-cells'
75 Clock gating node shown as "Clock stop processing block" in the
76 fig. "Clock System Overview" of the manual.
77 Registers are "xxx clock gate control register" (XXXGCLKCTRL).
81 const: renesas,emev2-smu-gclk
91 '#clock-cells':
95 - compatible
96 - reg
97 - clocks
98 - '#clock-cells'
105 - |
106 // Example of clock-tree description:
108 // This describes a clock path in the clock tree
109 // c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
111 compatible = "renesas,emev2-smu";
113 #address-cells = <2>;
114 #size-cells = <0>;
117 compatible = "fixed-clock";
118 clock-frequency = <32768>;
119 #clock-cells = <0>;
122 compatible = "fixed-factor-clock";
124 clock-div = <1>;
125 clock-mult = <7000>;
126 #clock-cells = <0>;
129 compatible = "renesas,emev2-smu-clkdiv";
132 #clock-cells = <0>;
135 compatible = "renesas,emev2-smu-gclk";
138 #clock-cells = <0>;