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/linux-6.12.1/Documentation/devicetree/bindings/power/
Dallwinner,sun20i-d1-ppu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/allwinner,sun20i-d1-ppu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner SoCs PPU power domain controller
10 - Samuel Holland <samuel@sholland.org>
13 D1 and related SoCs contain a power domain controller for the CPUs, GPU, and
14 video-related hardware.
19 - allwinner,sun20i-d1-ppu
31 '#power-domain-cells':
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/linux-6.12.1/drivers/pmdomain/sunxi/
Dsun20i-ppu.c1 // SPDX-License-Identifier: GPL-2.0-only
53 u32 status = readl(pd->base + PD_STATUS_REG); in sun20i_ppu_pd_is_on()
67 ret = readl_poll_timeout(pd->base + PD_STATUS_REG, status, in sun20i_ppu_pd_set_power()
73 writel(state, pd->base + PD_COMMAND_REG); in sun20i_ppu_pd_set_power()
76 ret = readl_poll_timeout(pd->base + PD_STATUS_REG, status, in sun20i_ppu_pd_set_power()
83 writel(status, pd->base + PD_STATUS_REG); in sun20i_ppu_pd_set_power()
105 struct device *dev = &pdev->dev; in sun20i_ppu_probe()
106 struct genpd_onecell_data *ppu; in sun20i_ppu_probe() local
115 return -EINVAL; in sun20i_ppu_probe()
117 pds = devm_kcalloc(dev, desc->num_domains, sizeof(*pds), GFP_KERNEL); in sun20i_ppu_probe()
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/linux-6.12.1/arch/riscv/boot/dts/allwinner/
Dsunxi-d1s-t113.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
4 #include <dt-bindings/clock/sun6i-rtc.h>
5 #include <dt-bindings/clock/sun8i-de2.h>
6 #include <dt-bindings/clock/sun8i-tcon-top.h>
7 #include <dt-bindings/clock/sun20i-d1-ccu.h>
8 #include <dt-bindings/clock/sun20i-d1-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/sun8i-de2.h>
11 #include <dt-bindings/reset/sun20i-d1-ccu.h>
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/linux-6.12.1/drivers/clk/sunxi-ng/
Dccu-sun20i-d1-r.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #include "ccu-sun20i-d1-r.h"
23 { .fw_name = "pll-periph" },
25 static SUNXI_CCU_MP_DATA_WITH_MUX(r_ahb_clk, "r-ahb",
33 static SUNXI_CCU_MP_DATA_WITH_MUX(r_apb0_clk, "r-apb0",
41 static SUNXI_CCU_GATE_HWS(bus_r_timer_clk, "bus-r-timer", &r_apb0_hw,
43 static SUNXI_CCU_GATE_HWS(bus_r_twd_clk, "bus-r-twd", &r_apb0_hw,
45 static SUNXI_CCU_GATE_HWS(bus_r_ppu_clk, "bus-r-ppu", &r_apb0_hw,
52 static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(r_ir_rx_clk, "r-ir-rx",
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