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/linux-6.12.1/Documentation/devicetree/bindings/sound/
Dfsl,ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/fsl,ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
13 Notes on fsl,playback-dma and fsl,capture-dma
14 On SOCs that have an SSI, specific DMA channels are hard-wired for playback
18 DMA controller to use, but the channels themselves are hard-wired. The
22 "fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
23 "fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
[all …]
Drenesas,rz-ssi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/renesas,rz-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/{G2L,V2L} ASoC Sound Serial Interface (SSIF-2)
10 - Biju Das <biju.das.jz@bp.renesas.com>
13 - $ref: dai-common.yaml#
18 - enum:
19 - renesas,r9a07g043-ssi # RZ/G2UL and RZ/Five
20 - renesas,r9a07g044-ssi # RZ/G2{L,LC}
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Deukrea-tlv320.txt5 - compatible : "eukrea,asoc-tlv320"
7 - eukrea,model : The user-visible name of this sound complex.
9 - ssi-controller : The phandle of the SSI controller.
11 - fsl,mux-int-port : The internal port of the i.MX audio muxer (AUDMUX).
13 - fsl,mux-ext-port : The external port of the i.MX audio muxer.
21 compatible = "eukrea,asoc-tlv320";
22 eukrea,model = "imx51-eukrea-tlv320aic23";
23 ssi-controller = <&ssi2>;
24 fsl,mux-int-port = <2>;
25 fsl,mux-ext-port = <3>;
Dfsl,imx-audio-es8328.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/fsl,imx-audio-es8328.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
14 - $ref: sound-card-common.yaml#
18 const: fsl,imx-audio-es8328
22 description: The user-visible name of this sound complex
24 ssi-controller:
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Dimx-audio-sgtl5000.txt5 - compatible : "fsl,imx-audio-sgtl5000"
7 - model : The user-visible name of this sound complex
9 - ssi-controller : The phandle of the i.MX SSI controller
11 - audio-codec : The phandle of the SGTL5000 audio codec
13 - audio-routing : A list of the connections between audio components.
35 - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
37 - mux-ext-port : The external port of the i.MX audio muxer
45 compatible = "fsl,imx51-babbage-sgtl5000",
46 "fsl,imx-audio-sgtl5000";
47 model = "imx51-babbage-sgtl5000";
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/linux-6.12.1/Documentation/devicetree/bindings/spi/
Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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/linux-6.12.1/Documentation/devicetree/bindings/hsi/
Domap-ssi.txt1 OMAP SSI controller bindings
3 OMAP3's Synchronous Serial Interface (SSI) controller implements a
5 while the controller found inside OMAP4 is supposed to be fully compliant
9 - compatible: Should include "ti,omap3-ssi" or "ti,omap4-hsi"
10 - reg-names: Contains the values "sys" and "gdd" (in this order).
11 - reg: Contains a matching register specifier for each entry
12 in reg-names.
13 - interrupt-names: Contains the value "gdd_mpu".
14 - interrupts: Contains matching interrupt information for each entry
15 in interrupt-names.
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/linux-6.12.1/drivers/hsi/controllers/
Domap_ssi.h1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* OMAP SSI internal interface.
23 #define SSI_BYTES_TO_FRAMES(x) ((((x) - 1) >> 2) + 1)
28 * struct omap_ssm_ctx - OMAP synchronous serial module (TX/RX) context
50 * struct omap_ssi_port - OMAP SSI port data
53 * @sst_dma: SSI transmitter physical base address
54 * @ssr_dma: SSI receiver physical base address
55 * @sst_base: SSI transmitter base address
56 * @ssr_base: SSI receiver base address
58 * @lock: Spin lock to serialize access to the SSI port
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Domap_ssi_core.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* OMAP SSI driver.
17 #include <linux/dma-mapping.h>
42 struct hsi_controller *ssi = m->private; in ssi_regs_show() local
43 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); in ssi_regs_show()
44 void __iomem *sys = omap_ssi->sys; in ssi_regs_show()
46 pm_runtime_get_sync(ssi->device.parent); in ssi_regs_show()
50 pm_runtime_put(ssi->device.parent); in ssi_regs_show()
57 struct hsi_controller *ssi = m->private; in ssi_gdd_regs_show() local
58 struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi); in ssi_gdd_regs_show()
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/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr8a7778.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M1A (R8A77781) SoC
14 #include <dt-bindings/clock/r8a7778-clock.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/interrupt-controller/irq.h>
20 interrupt-parent = <&gic>;
21 #address-cells = <1>;
22 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
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Dr8a7794.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car E2 (R8A77940) SoC
9 #include <dt-bindings/clock/r8a7794-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a7794-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
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Dr8a7793.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M2-N (R8A77930) SoC
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
8 #include <dt-bindings/clock/r8a7793-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/power/r8a7793-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
37 compatible = "fixed-clock";
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Dr8a7745.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Cogent Embedded Inc.
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
11 #include <dt-bindings/power/r8a7745-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
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Dr8a7743.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Cogent Embedded Inc.
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a7743-cpg-mssr.h>
11 #include <dt-bindings/power/r8a7743-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
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Dr8a7744.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a7744-cpg-mssr.h>
11 #include <dt-bindings/power/r8a7744-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
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Dr8a7791.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M2-W (R8A77910) SoC
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
10 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/power/r8a7791-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
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Dr8a7790.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H2 (R8A77900) SoC
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
10 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/power/r8a7790-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
46 compatible = "fixed-clock";
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Dr8a7742.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/r8a7742-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/power/r8a7742-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
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/linux-6.12.1/sound/soc/fsl/
Dfsl_dma.c1 // SPDX-License-Identifier: GPL-2.0
7 // Copyright 2007-2010 Freescale Semiconductor, Inc.
9 // This driver implements ASoC support for the Elo DMA controller, which is
10 // the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
16 #include <linux/dma-mapping.h>
39 * The formats that the DMA controller supports, which is anything
72 /** fsl_dma_private: p-substream DMA data
74 * Each substream has a 1-to-1 association with a DMA channel.
76 * The link[] array is first because it needs to be aligned on a 32-byte
112 * The PCM hardware is the Freescale DMA controller. This structure defines
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Dp1022_rdk.c1 // SPDX-License-Identifier: GPL-2.0
28 /* P1022-specific PMUXCR and DMUXCR bit definitions */
37 #define CCSR_GUTS_DMUXCR_PAD 1 /* DMA controller/channel set to pad */
38 #define CCSR_GUTS_DMUXCR_SSI 2 /* DMA controller/channel set to SSI */
44 * channel on each DMA controller. Rather than have a bunch of repetitive
49 * co: The DMA controller (0 or 1)
50 * ch: The channel on the DMA controller (0, 1, 2, or 3)
56 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch)); in guts_set_dmuxcr()
58 clrsetbits_be32(&guts->dmuxcr, 3 << shift, device << shift); in guts_set_dmuxcr()
65 * machine_data: machine-specific ASoC device data
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/linux-6.12.1/arch/mips/boot/dts/ingenic/
Dcu1000-neo.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/ingenic,sysost.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "yna,cu1000-neo", "ingenic,x1000e";
11 model = "YSH & ATIL General Board CU1000-Neo";
18 stdout-path = "serial2:115200n8";
27 compatible = "gpio-leds";
28 led-0 {
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/linux-6.12.1/arch/arm/boot/dts/nxp/imx/
Dimx50.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #include "imx50-pinfunc.h"
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/imx5-clock.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 * pre-existing /chosen node to be available to insert the
47 #address-cells = <1>;
48 #size-cells = <0>;
51 compatible = "arm,cortex-a8";
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Dimx53.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include "imx53-pinfunc.h"
7 #include <dt-bindings/clock/imx5-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 * pre-existing /chosen node to be available to insert the
50 #address-cells = <1>;
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/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr8a774c0.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <0>;
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/linux-6.12.1/drivers/spi/
Dspi-dw.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/spi/spi-mem.h>
14 /* Synopsys DW SSI IP-core virtual IDs */
18 /* Synopsys DW SSI component versions (FourCC sequence) */
21 /* DW SSI IP-core ID and version check helpers */
23 ((_dws)->ip == DW_ ## _ip ## _ID)
26 (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)
32 /* DW SPI controller capabilities */
36 /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
65 /* Bit fields in CTRLR0 (DWC APB SSI) */
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