drivers/spi/spi-dw.h

1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/spi/spi-mem.h>
14 /* Synopsys DW SSI IP-core virtual IDs */
18 /* Synopsys DW SSI component versions (FourCC sequence) */
21 /* DW SSI IP-core ID and version check helpers */
23 	((_dws)->ip == DW_ ## _ip ## _ID)
26 	(dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)
32 /* DW SPI controller capabilities */
36 /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
65 /* Bit fields in CTRLR0 (DWC APB SSI) */
89 /* Bit fields in CTRLR0 (DWC SSI with AHB interface) */
154 	u32			ip;		/* Synopsys DW SSI IP-core ID */
163 	u32			max_mem_freq;	/* max mem-ops bus freq */
207 	return __raw_readl(dws->regs + offset);  in dw_readl()
212 	__raw_writel(val, dws->regs + offset);  in dw_writel()
217 	switch (dws->reg_io_width) {  in dw_read_io_reg()
219 		return readw_relaxed(dws->regs + offset);  in dw_read_io_reg()
222 		return readl_relaxed(dws->regs + offset);  in dw_read_io_reg()
228 	switch (dws->reg_io_width) {  in dw_write_io_reg()
230 		writew_relaxed(val, dws->regs + offset);  in dw_write_io_reg()
234 		writel_relaxed(val, dws->regs + offset);  in dw_write_io_reg()
268  * This disables the SPI controller, interrupts, clears the interrupts status
269  * and CS, then re-enables the controller back. Transmit and receive FIFO