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/linux-6.12.1/Documentation/devicetree/bindings/media/
Dmediatek,vcodec-subdev-decoder.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yunfei Dong <yunfei.dong@mediatek.com>
20 +------------------------------------------------+-------------------------------------+
22 | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
24 +------------||-------------||-------------------+---------------------||--------------+
26 -------------||-------------||-------------------|---------------------||---------------
27 ||<------------||----------------HW index---------------->|| <child>
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/soc/mediatek/
Dscpsys.txt11 power/power-domain.yaml. It provides the power domains defined in
12 - include/dt-bindings/power/mt8173-power.h
13 - include/dt-bindings/power/mt6797-power.h
14 - include/dt-bindings/power/mt6765-power.h
15 - include/dt-bindings/power/mt2701-power.h
16 - include/dt-bindings/power/mt2712-power.h
17 - include/dt-bindings/power/mt7622-power.h
20 - compatible: Should be one of:
21 - "mediatek,mt2701-scpsys"
22 - "mediatek,mt2712-scpsys"
[all …]
/linux-6.12.1/drivers/media/platform/mediatek/vcodec/decoder/
Dmtk_vcodec_dec_hw.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 * enum mtk_vdec_hw_reg_idx - subdev hardware register base index
25 * @VDEC_HW_SYS : vdec soc register index
26 * @VDEC_HW_MISC: vdec misc register index
27 * @VDEC_HW_MAX : vdec supported max register index
36 * struct mtk_vdec_hw_dev - vdec hardware driver data
Dmtk_vcodec_dec_hw.c1 // SPDX-License-Identifier: GPL-2.0
22 .compatible = "mediatek,mtk-vcodec-lat",
26 .compatible = "mediatek,mtk-vcodec-core",
30 .compatible = "mediatek,mtk-vcodec-lat-soc",
39 struct platform_device *pdev = vdec_dev->plat_dev; in mtk_vdec_hw_prob_done()
48 of_id->compatible); in mtk_vdec_hw_prob_done()
54 hw_idx = (enum mtk_vdec_hw_id)(uintptr_t)of_id->data; in mtk_vdec_hw_prob_done()
55 if (!test_bit(hw_idx, vdec_dev->subdev_bitmap)) { in mtk_vdec_hw_prob_done()
56 dev_err(&pdev->dev, "vdec %d is not ready", hw_idx); in mtk_vdec_hw_prob_done()
57 return -EAGAIN; in mtk_vdec_hw_prob_done()
[all …]
/linux-6.12.1/drivers/staging/media/meson/vdec/
Dvdec.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 #include <media/videobuf2-v4l2.h>
14 #include <media/v4l2-ctrls.h>
15 #include <media/v4l2-device.h>
16 #include <linux/soc/amlogic/meson-canvas.h>
20 /* 32 buffers in 3-plane YUV420 */
29 * struct amvdec_timestamp - stores a src timestamp along with a VIFIFO offset
50 * struct amvdec_core - device parameters, singleton
57 * @platform: platform-specific data
97 * struct amvdec_ops - vdec operations
[all …]
/linux-6.12.1/Documentation/admin-guide/perf/
Dmeson-ddr-pmu.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Amlogic SoC DDR Bandwidth Performance Monitoring Unit (PMU)
7 The Amlogic Meson G12 SoC contains a bandwidth monitor inside DRAM controller.
20 meson_ddr_bw/chan_{1,2,3,4}_rw_bytes/ events are channel-specific events.
22 individual IP module in SoC.
26 + arm - from CPU
27 + vpu_read1 - from OSD + VPP read
28 + gpu - from 3D GPU
29 + pcie - from PCIe controller
30 + hdcp - from HDCP controller
[all …]
/linux-6.12.1/drivers/pmdomain/mediatek/
Dmtk-scpsys.c1 // SPDX-License-Identifier: GPL-2.0-only
14 #include <linux/soc/mediatek/infracfg.h>
16 #include <dt-bindings/power/mt2701-power.h>
17 #include <dt-bindings/power/mt2712-power.h>
18 #include <dt-bindings/power/mt6797-power.h>
19 #include <dt-bindings/power/mt7622-power.h>
20 #include <dt-bindings/power/mt7623a-power.h>
21 #include <dt-bindings/power/mt8173-power.h>
28 #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x))
102 "vdec",
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/linux-6.12.1/drivers/media/platform/verisilicon/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
22 will be called hantro-vpu.
41 bool "Hantro VDEC SAMA5D4 support"
62 Enable support for H6 SoC.
/linux-6.12.1/drivers/clk/mediatek/
Dclk-mt8188-vdec.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
8 #include <linux/clk-provider.h>
11 #include "clk-gate.h"
12 #include "clk-mtk.h"
76 { .compatible = "mediatek,mt8188-vdecsys-soc", .data = &vdec1_desc },
77 { .compatible = "mediatek,mt8188-vdecsys", .data = &vdec2_desc },
86 .name = "clk-mt8188-vdec",
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
5 menu "Clock driver for MediaTek SoC"
353 required on MediaTek MT7622 SoC.
360 to PCI-E and USB.
383 required on MediaTek MT7629 SoC.
390 to PCI-E and USB.
399 required for various peripherals found on this SoC.
407 required on MediaTek MT7981 SoC.
424 required on MediaTek MT7986 SoC.
433 required for various periperals found on this SoC.
[all …]
/linux-6.12.1/arch/arm64/boot/dts/mediatek/
Dmt8167.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt8167-clk.h>
9 #include <dt-bindings/memory/mt8167-larb-port.h>
10 #include <dt-bindings/power/mt8167-power.h>
12 #include "mt8167-pinfunc.h"
19 soc {
21 compatible = "mediatek,mt8167-topckgen", "syscon";
23 #clock-cells = <1>;
27 compatible = "mediatek,mt8167-infracfg", "syscon";
29 #clock-cells = <1>;
[all …]
Dmt8192.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8192-clk.h>
9 #include <dt-bindings/gce/mt8192-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8192-larb-port.h>
13 #include <dt-bindings/pinctrl/mt8192-pinfunc.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/power/mt8192-power.h>
[all …]
Dmt8186.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
[all …]
Dmt8188.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 /dts-v1/;
8 #include <dt-bindings/clock/mediatek,mt8188-clk.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/mailbox/mediatek,mt8188-gce.h>
12 #include <dt-bindings/phy/phy.h>
13 #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>
14 #include <dt-bindings/power/mediatek,mt8188-power.h>
15 #include <dt-bindings/reset/mt8188-resets.h>
[all …]
/linux-6.12.1/arch/arm64/boot/dts/amlogic/
Dmeson-gxbb.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include "meson-gx.dtsi"
7 #include "meson-gx-mali450.dtsi"
8 #include <dt-bindings/gpio/meson-gxbb-gpio.h>
9 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
10 #include <dt-bindings/clock/gxbb-clkc.h>
11 #include <dt-bindings/clock/gxbb-aoclkc.h>
12 #include <dt-bindings/reset/gxbb-aoclkc.h>
15 compatible = "amlogic,meson-gxbb";
17 soc {
[all …]
Dmeson-gxl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
16 soc {
18 compatible = "amlogic,meson-gxl-usb-ctrl";
21 #address-cells = <2>;
[all …]
Dmeson-gx.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/power/meson-gxbb-power.h>
16 #include <dt-bindings/thermal/thermal.h>
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
29 reserved-memory {
[all …]
/linux-6.12.1/include/dt-bindings/memory/
Dmediatek,mt8188-memory-port.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
9 #include <dt-bindings/memory/mtk-memory-port.h>
51 * This is the suggested mapping in this SoC:
53 * modules dma-address-region larbs-ports
61 * This SoC have two MM IOMMU HWs, this is the connected information:
62 * iommu-vdo: larb0/2/5/9/10/11A/11C/13/16B/17B/19/21
63 * iommu-vpp: larb1/3/4/6/7/11B/12/14/15/16A/17A/23/27
69 /* LARB 0 -- VDO-0 */
78 /* LARB 1 -- VD0-0 */
87 /* LARB 2 -- VDO-1 */
[all …]
Dmt8186-memory-port.h1 /* SPDX-License-Identifier: GPL-2.0-only */
11 #include <dt-bindings/memory/mtk-memory-port.h>
20 * This is the suggested mapping in this SoC:
22 * modules dma-address-region larbs-ports
32 /* LARB 0 -- MMSYS */
38 /* LARB 1 -- MMSYS */
45 /* LARB 2 -- MMSYS */
52 /* LARB 4 -- VDEC */
68 /* LARB 7 -- VENC */
83 /* LARB 8 -- WPE */
[all …]
/linux-6.12.1/drivers/soc/amlogic/
Dmeson-clk-measure.c1 // SPDX-License-Identifier: GPL-2.0+
128 CLK_MSR_ID(32, "vdec"),
277 CLK_MSR_ID(32, "vdec"),
394 CLK_MSR_ID(32, "vdec"),
494 struct meson_msr *priv = clk_msr_id->priv; in meson_measure_id()
502 regmap_write(priv->regmap, MSR_CLK_REG0, 0); in meson_measure_id()
505 regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_DURATION, in meson_measure_id()
506 FIELD_PREP(MSR_DURATION, duration - 1)); in meson_measure_id()
509 regmap_update_bits(priv->regmap, MSR_CLK_REG0, MSR_CLK_SRC, in meson_measure_id()
510 FIELD_PREP(MSR_CLK_SRC, clk_msr_id->id)); in meson_measure_id()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/soc/tegra/
Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
19 - nvidia,tegra124-pmc
[all …]
/linux-6.12.1/drivers/perf/amlogic/
Dmeson_g12_ddr_pmu.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <soc/amlogic/meson_ddr_pmu.h>
43 PMU_FORMAT_ATTR(event, "config:0-7");
58 PMU_FORMAT_ATTR(vdec, "config1:21");
135 val = readl(info->pll_reg); in dmc_g12_get_freq_quick()
179 r = readl(db->ddr_reg[0] + (DMC_MON_G12_CTRL0 + (i << 2))); in g12_dump_reg()
182 r = readl(db->ddr_reg[0] + DMC_MON_G12_ALL_REQ_CNT); in g12_dump_reg()
184 r = readl(db->ddr_reg[0] + DMC_MON_G12_ALL_GRANT_CNT); in g12_dump_reg()
186 r = readl(db->ddr_reg[0] + DMC_MON_G12_ONE_GRANT_CNT); in g12_dump_reg()
188 r = readl(db->ddr_reg[0] + DMC_MON_G12_SEC_GRANT_CNT); in g12_dump_reg()
[all …]
/linux-6.12.1/drivers/soc/tegra/
Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
52 #include <soc/tegra/common.h>
53 #include <soc/tegra/fuse.h>
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/
Drk3328.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
[all …]
/linux-6.12.1/drivers/pmdomain/rockchip/
Dpm-domains.c1 // SPDX-License-Identifier: GPL-2.0-only
22 #include <soc/rockchip/pm_domains.h>
23 #include <dt-bindings/power/px30-power.h>
24 #include <dt-bindings/power/rockchip,rv1126-power.h>
25 #include <dt-bindings/power/rk3036-power.h>
26 #include <dt-bindings/power/rk3066-power.h>
27 #include <dt-bindings/power/rk3128-power.h>
28 #include <dt-bindings/power/rk3188-power.h>
29 #include <dt-bindings/power/rk3228-power.h>
30 #include <dt-bindings/power/rk3288-power.h>
[all …]

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