Searched +full:sg2042 +full:- +full:rpgate (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-rpgate.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: Sophgo SG2042 Gate Clock Generator for RP(riscv processors) subsystem10 - Chen Wang <unicorn_wang@outlook.com>14 const: sophgo,sg2042-rpgate21 - description: Gate clock for RP subsystem23 clock-names:25 - const: rpgate[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Sophgo SG2042 RP clock Driver10 #include <linux/clk-provider.h>13 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>15 #include "clk-sg2042.h"18 #define R_RP_RXU_CLK_ENABLE (0x0368 - R_SYSGATE_BEGIN)19 #define R_MP0_STATUS_REG (0x0380 - R_SYSGATE_BEGIN)20 #define R_MP0_CONTROL_REG (0x0384 - R_SYSGATE_BEGIN)21 #define R_MP1_STATUS_REG (0x0388 - R_SYSGATE_BEGIN)22 #define R_MP1_CONTROL_REG (0x038C - R_SYSGATE_BEGIN)[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-$(CONFIG_CLK_SOPHGO_CV1800) += clk-sophgo-cv1800.o4 clk-sophgo-cv1800-y += clk-cv1800.o5 clk-sophgo-cv1800-y += clk-cv18xx-common.o6 clk-sophgo-cv1800-y += clk-cv18xx-ip.o7 clk-sophgo-cv1800-y += clk-cv18xx-pll.o9 obj-$(CONFIG_CLK_SOPHGO_SG2042_CLKGEN) += clk-sg2042-clkgen.o10 obj-$(CONFIG_CLK_SOPHGO_SG2042_PLL) += clk-sg2042-pll.o11 obj-$(CONFIG_CLK_SOPHGO_SG2042_RPGATE) += clk-sg2042-rpgate.o
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)6 /dts-v1/;7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>10 #include <dt-bindings/interrupt-controller/irq.h>11 #include <dt-bindings/reset/sophgo,sg2042-reset.h>13 #include "sg2042-cpus.dtsi"16 compatible = "sophgo,sg2042";17 #address-cells = <2>;[all …]