clk/sophgo/clk-sg2042-rpgate.c

1 // SPDX-License-Identifier: GPL-2.0
3  * Sophgo SG2042 RP clock Driver
10 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
15 #include "clk-sg2042.h"
18 #define R_RP_RXU_CLK_ENABLE	(0x0368 - R_SYSGATE_BEGIN)
19 #define R_MP0_STATUS_REG	(0x0380 - R_SYSGATE_BEGIN)
20 #define R_MP0_CONTROL_REG	(0x0384 - R_SYSGATE_BEGIN)
21 #define R_MP1_STATUS_REG	(0x0388 - R_SYSGATE_BEGIN)
22 #define R_MP1_CONTROL_REG	(0x038C - R_SYSGATE_BEGIN)
23 #define R_MP2_STATUS_REG	(0x0390 - R_SYSGATE_BEGIN)
24 #define R_MP2_CONTROL_REG	(0x0394 - R_SYSGATE_BEGIN)
25 #define R_MP3_STATUS_REG	(0x0398 - R_SYSGATE_BEGIN)
26 #define R_MP3_CONTROL_REG	(0x039C - R_SYSGATE_BEGIN)
27 #define R_MP4_STATUS_REG	(0x03A0 - R_SYSGATE_BEGIN)
28 #define R_MP4_CONTROL_REG	(0x03A4 - R_SYSGATE_BEGIN)
29 #define R_MP5_STATUS_REG	(0x03A8 - R_SYSGATE_BEGIN)
30 #define R_MP5_CONTROL_REG	(0x03AC - R_SYSGATE_BEGIN)
31 #define R_MP6_STATUS_REG	(0x03B0 - R_SYSGATE_BEGIN)
32 #define R_MP6_CONTROL_REG	(0x03B4 - R_SYSGATE_BEGIN)
33 #define R_MP7_STATUS_REG	(0x03B8 - R_SYSGATE_BEGIN)
34 #define R_MP7_CONTROL_REG	(0x03BC - R_SYSGATE_BEGIN)
35 #define R_MP8_STATUS_REG	(0x03C0 - R_SYSGATE_BEGIN)
36 #define R_MP8_CONTROL_REG	(0x03C4 - R_SYSGATE_BEGIN)
37 #define R_MP9_STATUS_REG	(0x03C8 - R_SYSGATE_BEGIN)
38 #define R_MP9_CONTROL_REG	(0x03CC - R_SYSGATE_BEGIN)
39 #define R_MP10_STATUS_REG	(0x03D0 - R_SYSGATE_BEGIN)
40 #define R_MP10_CONTROL_REG	(0x03D4 - R_SYSGATE_BEGIN)
41 #define R_MP11_STATUS_REG	(0x03D8 - R_SYSGATE_BEGIN)
42 #define R_MP11_CONTROL_REG	(0x03DC - R_SYSGATE_BEGIN)
43 #define R_MP12_STATUS_REG	(0x03E0 - R_SYSGATE_BEGIN)
44 #define R_MP12_CONTROL_REG	(0x03E4 - R_SYSGATE_BEGIN)
45 #define R_MP13_STATUS_REG	(0x03E8 - R_SYSGATE_BEGIN)
46 #define R_MP13_CONTROL_REG	(0x03EC - R_SYSGATE_BEGIN)
47 #define R_MP14_STATUS_REG	(0x03F0 - R_SYSGATE_BEGIN)
48 #define R_MP14_CONTROL_REG	(0x03F4 - R_SYSGATE_BEGIN)
49 #define R_MP15_STATUS_REG	(0x03F8 - R_SYSGATE_BEGIN)
50 #define R_MP15_CONTROL_REG	(0x03FC - R_SYSGATE_BEGIN)
53  * struct sg2042_rpgate_clock - Gate clock for RP(riscv processors) subsystem
90 	SG2042_GATE_FW(GATE_CLK_RXU0, "clk_gate_rxu0", "rpgate",
92 	SG2042_GATE_FW(GATE_CLK_RXU1, "clk_gate_rxu1", "rpgate",
94 	SG2042_GATE_FW(GATE_CLK_RXU2, "clk_gate_rxu2", "rpgate",
96 	SG2042_GATE_FW(GATE_CLK_RXU3, "clk_gate_rxu3", "rpgate",
98 	SG2042_GATE_FW(GATE_CLK_RXU4, "clk_gate_rxu4", "rpgate",
100 	SG2042_GATE_FW(GATE_CLK_RXU5, "clk_gate_rxu5", "rpgate",
102 	SG2042_GATE_FW(GATE_CLK_RXU6, "clk_gate_rxu6", "rpgate",
104 	SG2042_GATE_FW(GATE_CLK_RXU7, "clk_gate_rxu7", "rpgate",
106 	SG2042_GATE_FW(GATE_CLK_RXU8, "clk_gate_rxu8", "rpgate",
108 	SG2042_GATE_FW(GATE_CLK_RXU9, "clk_gate_rxu9", "rpgate",
110 	SG2042_GATE_FW(GATE_CLK_RXU10, "clk_gate_rxu10", "rpgate",
112 	SG2042_GATE_FW(GATE_CLK_RXU11, "clk_gate_rxu11", "rpgate",
114 	SG2042_GATE_FW(GATE_CLK_RXU12, "clk_gate_rxu12", "rpgate",
116 	SG2042_GATE_FW(GATE_CLK_RXU13, "clk_gate_rxu13", "rpgate",
118 	SG2042_GATE_FW(GATE_CLK_RXU14, "clk_gate_rxu14", "rpgate",
120 	SG2042_GATE_FW(GATE_CLK_RXU15, "clk_gate_rxu15", "rpgate",
122 	SG2042_GATE_FW(GATE_CLK_RXU16, "clk_gate_rxu16", "rpgate",
124 	SG2042_GATE_FW(GATE_CLK_RXU17, "clk_gate_rxu17", "rpgate",
126 	SG2042_GATE_FW(GATE_CLK_RXU18, "clk_gate_rxu18", "rpgate",
128 	SG2042_GATE_FW(GATE_CLK_RXU19, "clk_gate_rxu19", "rpgate",
130 	SG2042_GATE_FW(GATE_CLK_RXU20, "clk_gate_rxu20", "rpgate",
132 	SG2042_GATE_FW(GATE_CLK_RXU21, "clk_gate_rxu21", "rpgate",
134 	SG2042_GATE_FW(GATE_CLK_RXU22, "clk_gate_rxu22", "rpgate",
136 	SG2042_GATE_FW(GATE_CLK_RXU23, "clk_gate_rxu23", "rpgate",
138 	SG2042_GATE_FW(GATE_CLK_RXU24, "clk_gate_rxu24", "rpgate",
140 	SG2042_GATE_FW(GATE_CLK_RXU25, "clk_gate_rxu25", "rpgate",
142 	SG2042_GATE_FW(GATE_CLK_RXU26, "clk_gate_rxu26", "rpgate",
144 	SG2042_GATE_FW(GATE_CLK_RXU27, "clk_gate_rxu27", "rpgate",
146 	SG2042_GATE_FW(GATE_CLK_RXU28, "clk_gate_rxu28", "rpgate",
148 	SG2042_GATE_FW(GATE_CLK_RXU29, "clk_gate_rxu29", "rpgate",
150 	SG2042_GATE_FW(GATE_CLK_RXU30, "clk_gate_rxu30", "rpgate",
152 	SG2042_GATE_FW(GATE_CLK_RXU31, "clk_gate_rxu31", "rpgate",
156 	SG2042_GATE_FW(GATE_CLK_MP0, "clk_gate_mp0", "rpgate",
158 	SG2042_GATE_FW(GATE_CLK_MP1, "clk_gate_mp1", "rpgate",
160 	SG2042_GATE_FW(GATE_CLK_MP2, "clk_gate_mp2", "rpgate",
162 	SG2042_GATE_FW(GATE_CLK_MP3, "clk_gate_mp3", "rpgate",
164 	SG2042_GATE_FW(GATE_CLK_MP4, "clk_gate_mp4", "rpgate",
166 	SG2042_GATE_FW(GATE_CLK_MP5, "clk_gate_mp5", "rpgate",
168 	SG2042_GATE_FW(GATE_CLK_MP6, "clk_gate_mp6", "rpgate",
170 	SG2042_GATE_FW(GATE_CLK_MP7, "clk_gate_mp7", "rpgate",
172 	SG2042_GATE_FW(GATE_CLK_MP8, "clk_gate_mp8", "rpgate",
174 	SG2042_GATE_FW(GATE_CLK_MP9, "clk_gate_mp9", "rpgate",
176 	SG2042_GATE_FW(GATE_CLK_MP10, "clk_gate_mp10", "rpgate",
178 	SG2042_GATE_FW(GATE_CLK_MP11, "clk_gate_mp11", "rpgate",
180 	SG2042_GATE_FW(GATE_CLK_MP12, "clk_gate_mp12", "rpgate",
182 	SG2042_GATE_FW(GATE_CLK_MP13, "clk_gate_mp13", "rpgate",
184 	SG2042_GATE_FW(GATE_CLK_MP14, "clk_gate_mp14", "rpgate",
186 	SG2042_GATE_FW(GATE_CLK_MP15, "clk_gate_mp15", "rpgate",
205 			 gate->hw.init->name,  in sg2042_clk_register_rpgates()
206 			 gate->hw.init->parent_data,  in sg2042_clk_register_rpgates()
207 			 gate->hw.init->flags,  in sg2042_clk_register_rpgates()
208 			 clk_data->iobase + gate->offset_enable,  in sg2042_clk_register_rpgates()
209 			 gate->bit_idx,  in sg2042_clk_register_rpgates()
213 			pr_err("failed to register clock %s\n", gate->hw.init->name);  in sg2042_clk_register_rpgates()
218 		clk_data->onecell_data.hws[gate->id] = hw;  in sg2042_clk_register_rpgates()
230 	clk_data = devm_kzalloc(&pdev->dev,  in sg2042_init_clkdata()
234 		return -ENOMEM;  in sg2042_init_clkdata()
236 	clk_data->iobase = devm_platform_ioremap_resource(pdev, 0);  in sg2042_init_clkdata()
237 	if (WARN_ON(IS_ERR(clk_data->iobase)))  in sg2042_init_clkdata()
238 		return PTR_ERR(clk_data->iobase);  in sg2042_init_clkdata()
240 	clk_data->onecell_data.num = num_clks;  in sg2042_init_clkdata()
259 	ret = sg2042_clk_register_rpgates(&pdev->dev, clk_data, sg2042_gate_rp,  in sg2042_rpgate_probe()
264 	return devm_of_clk_add_hw_provider(&pdev->dev,  in sg2042_rpgate_probe()
266 					   &clk_data->onecell_data);  in sg2042_rpgate_probe()
274 	{ .compatible = "sophgo,sg2042-rpgate" },
282 		.name = "clk-sophgo-sg2042-rpgate",
290 MODULE_DESCRIPTION("Sophgo SG2042 rp subsystem clock driver");