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Searched +full:sg2042 +full:- +full:pll (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/drivers/clk/sophgo/
DKconfig1 # SPDX-License-Identifier: GPL-2.0
14 tristate "Sophgo SG2042 PLL clock support"
17 This driver supports the PLL clock controller on the
18 Sophgo SG2042 SoC. This clock IP uses three oscillators with
20 PLL, DDR PLL 0 and DDR PLL 1 respectively.
23 tristate "Sophgo SG2042 Clock Generator support"
27 Sophgo SG2042 SoC. This clock IP depends on SG2042 PLL clock
28 because it uses PLL clocks as input.
32 tristate "Sophgo SG2042 RP subsystem clock controller support"
36 controller on the Sophgo SG2042 SoC.
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_CLK_SOPHGO_CV1800) += clk-sophgo-cv1800.o
4 clk-sophgo-cv1800-y += clk-cv1800.o
5 clk-sophgo-cv1800-y += clk-cv18xx-common.o
6 clk-sophgo-cv1800-y += clk-cv18xx-ip.o
7 clk-sophgo-cv1800-y += clk-cv18xx-pll.o
9 obj-$(CONFIG_CLK_SOPHGO_SG2042_CLKGEN) += clk-sg2042-clkgen.o
10 obj-$(CONFIG_CLK_SOPHGO_SG2042_PLL) += clk-sg2042-pll.o
11 obj-$(CONFIG_CLK_SOPHGO_SG2042_RPGATE) += clk-sg2042-rpgate.o
Dclk-sg2042-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * Sophgo SG2042 PLL clock Driver
12 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
20 #include "clk-sg2042.h"
24 #define R_PLL_STAT (0xC0 - R_PLL_BEGIN)
25 #define R_PLL_CLKEN_CONTROL (0xC4 - R_PLL_BEGIN)
26 #define R_MPLL_CONTROL (0xE8 - R_PLL_BEGIN)
27 #define R_FPLL_CONTROL (0xF4 - R_PLL_BEGIN)
28 #define R_DPLL0_CONTROL (0xF8 - R_PLL_BEGIN)
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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dsophgo,sg2042-pll.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo SG2042 PLL Clock Generator
10 - Chen Wang <unicorn_wang@outlook.com>
14 const: sophgo,sg2042-pll
21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
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Dsophgo,sg2042-clkgen.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo SG2042 Clock Generator for divider/mux/gate
10 - Chen Wang <unicorn_wang@outlook.com>
14 const: sophgo,sg2042-clkgen
21 - description: Main PLL
22 - description: Fixed PLL
23 - description: DDR PLL 0
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/linux-6.12.1/arch/riscv/boot/dts/sophgo/
Dsg2042.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
13 #include "sg2042-cpus.dtsi"
16 compatible = "sophgo,sg2042";
17 #address-cells = <2>;
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