bindings/clock/sophgo%2Csg2042-pll.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/sophgo,sg2042-pll.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Sophgo SG2042 PLL Clock Generator
10   - Chen Wang <unicorn_wang@outlook.com>
14     const: sophgo,sg2042-pll
21       - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22       - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23       - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
25   clock-names:
27       - const: cgi_main
28       - const: cgi_dpll0
29       - const: cgi_dpll1
31   '#clock-cells':
34       See <dt-bindings/clock/sophgo,sg2042-pll.h> for valid indices.
37   - compatible
38   - reg
39   - clocks
40   - clock-names
41   - '#clock-cells'
46   - |
47     clock-controller@10000000 {
48       compatible = "sophgo,sg2042-pll";
51       clock-names = "cgi_main", "cgi_dpll0", "cgi_dpll1";
52       #clock-cells = <1>;