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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dmvebu-gated-clock.txt12 -----------------------------------
18 5 pex0 PCIe Cntrl 0
21 17 sdio SDHCI Host
29 -----------------------------------
33 5 pex0 PCIe 0 Clock out
40 17 sdio SDHCI Host
56 -----------------------------------
61 5 pex1 PCIe 1
83 -----------------------------------
84 5 pex1 PCIe 1
[all …]
/linux-6.12.1/drivers/mmc/host/
Dsdhci-of-hlwd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/mmc/host/sdhci-of-hlwd.c
9 * Based on sdhci-of-esdhc.c
21 #include "sdhci-pltfm.h"
24 * Ops and quirks for the Nintendo Wii SDHCI controllers.
30 #define SDHCI_HLWD_WRITE_DELAY 5 /* usecs */
75 { .compatible = "nintendo,hollywood-sdhci" },
82 .name = "sdhci-hlwd",
93 MODULE_DESCRIPTION("Nintendo Wii SDHCI OF driver");
Dsdhci-omap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * SDHCI Controller driver for TI's OMAP SoCs
11 #include <linux/mmc/slot-gpio.h>
23 #include "sdhci-pltfm.h"
33 #define CON_DW8 BIT(5)
97 /* sdhci-omap controller flags */
103 u32 offset; /* Offset for SDHCI regs from base */
142 return readl(host->base + host->omap_offset + offset); in sdhci_omap_readl()
148 writel(data, host->base + host->omap_offset + offset); in sdhci_omap_writel()
155 struct device *dev = omap_host->dev; in sdhci_omap_set_pbias()
[all …]
Dsdhci-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
20 #include <linux/mmc/slot-gpio.h>
32 #include "sdhci-cqhci.h"
33 #include "sdhci-pltfm.h"
42 #define SDHCI_CLOCK_CTRL_SDR50_TUNING_OVERRIDE BIT(5)
106 #define NVQUIRK_ENABLE_DDR50 BIT(5)
192 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_readw()
194 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && in tegra_sdhci_readw()
200 return readw(host->ioaddr + reg); in tegra_sdhci_readw()
[all …]
Dsdhci-of-ma35d1.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Shan-Chun Hung <shanchun1218@gmail.com>
16 #include <linux/dma-mapping.h>
32 #include "sdhci-pltfm.h"
33 #include "sdhci.h"
77 if (likely(!len || (ALIGN(addr, SZ_128M) == ALIGN(addr + len - 1, SZ_128M)))) { in ma35_adma_write_desc()
82 offset = addr & (SZ_128M - 1); in ma35_adma_write_desc()
83 tmplen = SZ_128M - offset; in ma35_adma_write_desc()
87 len -= tmplen; in ma35_adma_write_desc()
115 switch (ios->signal_voltage) { in ma35_start_signal_voltage_switch()
[all …]
Dsdhci-xenon.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Date: 2016-8-24
22 #include <linux/dma-mapping.h>
24 #include "sdhci-pltfm.h"
25 #include "sdhci-xenon.h"
44 dev_err(mmc_dev(host->mmc), "Internal clock never stabilised.\n"); in xenon_enable_internal_clk()
45 return -ETIMEDOUT; in xenon_enable_internal_clk()
53 /* Set SDCLK-off-while-idle */
94 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in xenon_enable_sdhc()
99 host->mmc->caps &= ~MMC_CAP_BUS_WIDTH_TEST; in xenon_enable_sdhc()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/mmc/
Dsamsung,s3c6410-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/samsung,s3c6410-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC SDHCI Controller
10 - Jaehoon Chung <jh80.chung@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
16 - samsung,s3c6410-sdhci
17 - samsung,exynos4210-sdhci
24 maxItems: 5
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Dsnps,dwcmshc-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
16 - items:
17 - const: rockchip,rk3576-dwcmshc
18 - const: rockchip,rk3588-dwcmshc
19 - enum:
[all …]
/linux-6.12.1/drivers/clk/samsung/
Dclk-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
17 #include "clk-pll.h"
98 /* S3C6400-specific parent clocks. */
103 /* S3C6410-specific parent clocks. */
142 MUX(MOUT_UHOST, "mout_uhost", uhost_p6400, CLK_SRC, 5, 2),
150 MUX(MOUT_UHOST, "mout_uhost", uhost_p6410, CLK_SRC, 5, 2),
216 GATE_BUS(HCLK_POST0, "hclk_post0", "hclk", HCLK_GATE, 5),
240 GATE_BUS(PCLK_WDT, "pclk_wdt", "pclk", PCLK_GATE, 5),
[all …]
/linux-6.12.1/arch/arm64/boot/dts/qcom/
Dsm6115p-lenovo-j606f.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
14 chassis-type = "tablet";
17 qcom,msm-id = <445 0x10000>, <420 0x10000>;
18 qcom,board-id = <34 3>;
25 #address-cells = <2>;
26 #size-cells = <2>;
29 framebuffer0: framebuffer@5c000000 {
30 compatible = "simple-framebuffer";
40 gpio-keys {
[all …]
/linux-6.12.1/arch/powerpc/boot/dts/
Dwii.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2008-2009 The GameCube Linux Team
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
15 * This is commented-out for now.
25 #address-cells = <1>;
26 #size-cells = <1>;
29 bootargs = "root=/dev/mmcblk0p2 rootwait udbg-immortal";
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dpinctrl_spear.txt4 - compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
9 - reg : Address range of the pinctrl registers
10 - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
11 - Its values for SPEAr300:
12 - NAND_MODE : <0>
13 - NOR_MODE : <1>
[all …]
/linux-6.12.1/arch/arm/boot/dts/nvidia/
Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
[all …]
Dtegra124.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/tegra124-car.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra124-peripherals-opp.dtsi"
[all …]
/linux-6.12.1/drivers/pinctrl/mediatek/
Dpinctrl-mt7621.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "pinctrl-mtmips.h"
14 #define MT7621_GPIO_MODE_UART2_SHIFT 5
40 FUNC("uart3", 0, 5, 4),
41 FUNC("i2s", 2, 5, 4),
42 FUNC("spdif3", 3, 5, 4),
49 static struct mtmips_pmx_func jtag_grp[] = { FUNC("jtag", 0, 13, 5) };
65 FUNC("sdhci", 0, 41, 8),
87 GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
99 { .compatible = "ralink,mt7621-pinctrl" },
[all …]
/linux-6.12.1/include/linux/platform_data/
Dpxa_sdhci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * PXA Platform - SDHCI platform data definitions
17 /* card always wired to host, like on-chip emmc */
19 /* Board design supports 8-bit data on SD/SDIO BUS */
23 * struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
26 * mmp2: each step is roughly 100ps, 5bits width
/linux-6.12.1/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
22 maxItems: 5
[all …]
/linux-6.12.1/drivers/phy/intel/
Dphy-intel-keembay-emmc.c1 // SPDX-License-Identifier: GPL-2.0-only
32 #define DLL_RDY_MASK BIT(5)
66 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
69 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in keembay_emmc_phy_power()
73 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK, in keembay_emmc_phy_power()
76 dev_err(&phy->dev, "turn off the dll failed: %d\n", ret); in keembay_emmc_phy_power()
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
107 udelay(5); in keembay_emmc_phy_power()
109 ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK, in keembay_emmc_phy_power()
[all …]
Dphy-intel-lgm-emmc.c1 // SPDX-License-Identifier: GPL-2.0
64 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
67 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
75 rate = clk_get_rate(priv->emmcclk); in intel_emmc_phy_power()
78 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); in intel_emmc_phy_power()
86 udelay(5); in intel_emmc_phy_power()
88 ret = regmap_update_bits(priv->syscfg, EMMC_PHYCTRL1_REG, PDB_MASK, in intel_emmc_phy_power()
91 dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret); in intel_emmc_phy_power()
96 * According to the user manual, it asks driver to wait 5us for in intel_emmc_phy_power()
102 ret = regmap_read_poll_timeout(priv->syscfg, EMMC_PHYSTAT_REG, in intel_emmc_phy_power()
[all …]
/linux-6.12.1/arch/arm/boot/dts/marvell/
Darmada-388-helios4.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
10 /dts-v1/;
11 #include "armada-388.dtsi"
12 #include "armada-38x-solidrun-microsom.dtsi"
25 /* So that mvebu u-boot can update the MAC addresses */
30 stdout-path = "serial0:115200n8";
33 reg_12v: regulator-12v {
34 compatible = "regulator-fixed";
35 regulator-name = "power_brick_12V";
36 regulator-min-microvolt = <12000000>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/st/
Dstih418-b2199.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "st,stih418-b2199", "st,stih418";
14 stdout-path = &sbc_serial0;
28 compatible = "gpio-leds";
29 led-red {
32 linux,default-trigger = "heartbeat";
34 led-green {
36 default-state = "off";
[all …]
Dstihxxx-b2120.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/clock/stih407-clks.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/media/c8sectpfe.h>
11 compatible = "gpio-leds";
12 led-red {
15 linux,default-trigger = "heartbeat";
17 led-green {
19 default-state = "off";
24 compatible = "simple-audio-card";
[all …]
/linux-6.12.1/arch/arm/boot/dts/samsung/
Ds3c64xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
16 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
32 #address-cells = <1>;
33 #size-cells = <0>;
37 compatible = "arm,arm1176jzf-s";
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/nvidia/
Dtegra132.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra124-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra124-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/thermal/tegra124-soctherm.h>
9 #include <dt-bindings/soc/tegra-pmc.h>
11 #include "tegra132-peripherals-opp.dtsi"
[all …]

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