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/linux-6.12.1/Documentation/devicetree/bindings/spi/ !
Dspi-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral-specific properties for a SPI bus.
11 be common properties like spi-max-frequency, spi-cpha, etc. or they could be
12 controller specific like delay in clock or data lines, etc. These properties
13 need to be defined in the peripheral node because they are per-peripheral and
19 - Mark Brown <broonie@kernel.org>
27 - minimum: 0
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Dsnps,dw-apb-ssi.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
13 - $ref: spi-controller.yaml#
14 - if:
19 - mscc,ocelot-spi
20 - mscc,jaguar2-spi
25 - if:
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Dspi-rockchip.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-rockchip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - $ref: spi-controller.yaml#
17 - Heiko Stuebner <heiko@sntech.de>
23 - const: rockchip,rk3036-spi
24 - const: rockchip,rk3066-spi
25 - const: rockchip,rk3228-spi
26 - const: rockchip,rv1108-spi
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/linux-6.12.1/drivers/iio/resolver/ !
Dad2s1200.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2018 David Veenstra <davidjulianveenstra@gmail.com>
7 * Copyright (c) 2010-2010 Analog Devices Inc.
11 #include <linux/delay.h>
32 * struct ad2s1200_state - driver instance specific data.
33 * @lock: protects both the GPIO pins and the rx buffer.
35 * @sample: GPIO pin SAMPLE.
37 * @rx: buffer for spi transfers.
42 struct gpio_desc *sample; member
44 __be16 rx __aligned(IIO_DMA_MINALIGN);
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Dad2s1210.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2010 Analog Devices Inc.
11 * ----------------------------|------|-------------------------------------------
23 * Resolution | D1:0 | *device tree: assigned-resolution-bits*
34 * ----------------------------------------|----|---------------------------------
52 #include <linux/delay.h>
142 /** GPIO pin connected to SAMPLE line. */
152 /* adi,fixed-mode property - only valid when mode_gpios == NULL. */
158 /** For reading raw sample value via SPI. */
162 } sample __aligned(IIO_DMA_MINALIGN);
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/linux-6.12.1/drivers/spi/ !
Dspi-dw-core.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
15 #include <linux/delay.h>
18 #include <linux/spi/spi-mem.h>
23 #include "spi-dw.h"
32 u32 rx_sample_dly; /* RX sample delay */
66 snprintf(name, 32, "dw_spi%d", dws->host->bus_num); in dw_spi_debugfs_init()
67 dws->debugfs = debugfs_create_dir(name, NULL); in dw_spi_debugfs_init()
69 dws->regset.regs = dw_spi_dbgfs_regs; in dw_spi_debugfs_init()
70 dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs); in dw_spi_debugfs_init()
[all …]
Dspi-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Addy Ke <addy.ke@rock-chips.com>
18 #define DRIVER_NAME "rockchip-spi"
67 /* ss_n to sclk_out delay */
158 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
180 void *rx; member
196 bool cs_high_supported; /* native CS supports active-high polarity */
203 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); in spi_enable_chip()
212 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_TARGET_TX_BUSY) && in wait_for_tx_idle()
213 !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))) in wait_for_tx_idle()
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/linux-6.12.1/arch/arm64/boot/dts/microchip/ !
Dsparx5_nand.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 cs14_pins: cs14-pins {
14 pinctrl-0 = <&si2_pins>;
15 pinctrl-names = "default";
17 compatible = "spi-mux";
18 mux-controls = <&mux>;
19 #address-cells = <1>;
20 #size-cells = <0>;
23 compatible = "spi-nand";
24 pinctrl-0 = <&cs14_pins>;
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/linux-6.12.1/Documentation/networking/ !
Dpktgen.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Enable CONFIG_NET_PKTGEN to compile and build pktgen either in-kernel
11 suitable sample script and configure that.
31 overload type of benchmarking, as this could hurt the normal use-case.
35 # ethtool -G ethX tx 1024
43 TX ring cause delay. Drivers usually delay cleaning up the
44 ring-buffers for various performance reasons, and packets stalling
48 (Intel 82599 chip). This driver (ixgbe) combines TX+RX ring cleanups,
49 and the cleanup interval is affected by the ethtool --coalesce setting
50 of parameter "rx-usecs".
[all …]
Dtimestamping.rst1 .. SPDX-License-Identifier: GPL-2.0
32 IP_MULTICAST_LOOP + SO_TIMESTAMP[NS]
43 -------------------------------------------------------------
59 -------------------------------------------------------------------
62 Its struct timespec allows for higher resolution (ns) timestamps than the
72 ----------------------------------------------------------------------
102 Request rx timestamps generated by the network adapter.
105 Request rx timestamps when data enters the kernel. These timestamps
122 transmit latency is, if long, often dominated by queuing delay. The
131 grained measurement of queuing delay. This flag can be enabled
[all …]
Dcan.rst2 SocketCAN - Controller Area Network
20 .. _socketcan-motivation:
29 functionality. Usually, there is only a hardware-specific device
32 Queueing of frames and higher-level transport protocols like ISO-TP
34 character-device implementations support only one single process to
47 protocol family module and also vice-versa. Also, the protocol family
57 communicate using a specific transport protocol, e.g. ISO-TP, just
60 CAN-IDs, frames, etc.
62 Similar functionality visible from user-space could be provided by a
74 * **Abstraction:** In most existing character-device implementations, the
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/linux-6.12.1/arch/arm/boot/dts/rockchip/ !
Drk3288-veyron.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/clock/rockchip,rk808.h>
9 #include <dt-bindings/input/input.h>
18 stdout-path = "serial2:115200n8";
31 power_button: power-button {
32 compatible = "gpio-keys";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pwr_key_l>;
36 key-power {
40 debounce-interval = <100>;
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Drv1108.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/rv1108-cru.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 interrupt-parent = <&gic>;
[all …]
Drk322x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3228-cru.h>
8 #include <dt-bindings/thermal/thermal.h>
9 #include <dt-bindings/power/rk3228-power.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/st/ !
Dstm32mp157c-phycore-stm32mp15-som.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * Copyright (C) 2022-2023 Steffen Trumtrar <kernel@pengutronix.de>
4 * Copyright (C) Phytec GmbH 2019-2020 - All Rights Reserved
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/leds/leds-pca9532.h>
14 #include <dt-bindings/mfd/st,stpmic1.h>
[all …]
/linux-6.12.1/arch/arm/boot/dts/allwinner/ !
Dsun8i-a83t.dtsi6 * This file is dual-licensed: you can use it either under the terms
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
48 #include <dt-bindings/clock/sun8i-de2.h>
49 #include <dt-bindings/clock/sun8i-r-ccu.h>
50 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
51 #include <dt-bindings/reset/sun8i-de2.h>
52 #include <dt-bindings/reset/sun8i-r-ccu.h>
53 #include <dt-bindings/thermal/thermal.h>
56 interrupt-parent = <&gic>;
[all …]
/linux-6.12.1/arch/arm/boot/dts/microchip/ !
Dsama7g5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
12 #include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include <dt-bindings/clock/at91.h>
16 #include <dt-bindings/dma/at91.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include <dt-bindings/mfd/at91-usart.h>
19 #include <dt-bindings/nvmem/microchip,sama7g5-otpc.h>
[all …]
/linux-6.12.1/drivers/net/phy/ !
Drealtek.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <linux/delay.h>
76 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
77 * is set, they cannot be accessed by C45-over-C22.
124 struct device *dev = &phydev->mdio.dev; in rtl821x_probe()
126 u32 phy_id = phydev->drv->phy_id; in rtl821x_probe()
131 return -ENOMEM; in rtl821x_probe()
133 priv->clk = devm_clk_get_optional_enabled(dev, NULL); in rtl821x_probe()
134 if (IS_ERR(priv->clk)) in rtl821x_probe()
135 return dev_err_probe(dev, PTR_ERR(priv->clk), in rtl821x_probe()
[all …]
/linux-6.12.1/arch/arm64/boot/dts/rockchip/ !
Drk3328.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
[all …]
Dpx30.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
[all …]
Drk356x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rk3568-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3568-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
[all …]
/linux-6.12.1/arch/arm64/boot/dts/ti/ !
Dk3-am69-sk.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/
9 /dts-v1/;
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include "k3-j784s4.dtsi"
16 compatible = "ti,am69-sk", "ti,j784s4";
20 stdout-path = "serial2:115200n8";
36 bootph-all;
42 reserved_memory: reserved-memory {
[all …]
Dk3-j721e-sk.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
5 * J721E SK URL: https://www.ti.com/tool/SK-TDA4VM
8 /dts-v1/;
10 #include "k3-j721e.dtsi"
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/net/ti-dp83867.h>
16 compatible = "ti,j721e-sk", "ti,j721e";
29 stdout-path = "serial2:115200n8";
[all …]
/linux-6.12.1/drivers/iio/adc/ !
Dstm32-adc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
16 #include <linux/iio/timer/stm32-lptim-trigger.h>
17 #include <linux/iio/timer/stm32-timer-trigger.h>
26 #include <linux/nvmem-consumer.h>
31 #include "stm32-adc-core.h"
58 /* extsel - trigger mux selection value */
84 STM32_ADC_INT_CH_NONE = -1,
[all …]
/linux-6.12.1/drivers/phy/rockchip/ !
Dphy-rockchip-usbdp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd
9 #include <dt-bindings/phy/phy.h>
13 #include <linux/delay.h>
115 /* u2phy-grf */
119 /* usb-grf */
123 /* usbdpphy-grf */
129 /* vo-grf */
179 bool hs; /* flag for high-speed */
204 /* voltage swing 0, pre-emphasis 0->3 */
[all …]

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