Lines Matching +full:rx +full:- +full:sample +full:- +full:delay +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0+
14 #include <linux/delay.h>
76 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
77 * is set, they cannot be accessed by C45-over-C22.
124 struct device *dev = &phydev->mdio.dev; in rtl821x_probe()
126 u32 phy_id = phydev->drv->phy_id; in rtl821x_probe()
131 return -ENOMEM; in rtl821x_probe()
133 priv->clk = devm_clk_get_optional_enabled(dev, NULL); in rtl821x_probe()
134 if (IS_ERR(priv->clk)) in rtl821x_probe()
135 return dev_err_probe(dev, PTR_ERR(priv->clk), in rtl821x_probe()
142 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); in rtl821x_probe()
143 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) in rtl821x_probe()
144 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; in rtl821x_probe()
146 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); in rtl821x_probe()
147 if (priv->has_phycr2) { in rtl821x_probe()
152 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; in rtl821x_probe()
153 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) in rtl821x_probe()
154 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; in rtl821x_probe()
157 phydev->priv = priv; in rtl821x_probe()
194 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8201_config_intr()
217 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8211b_config_intr()
239 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8211e_config_intr()
262 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8211f_config_intr()
352 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { in rtl8211_config_aneg()
372 struct rtl821x_priv *priv = phydev->priv; in rtl8211f_config_init()
373 struct device *dev = &phydev->mdio.dev; in rtl8211f_config_init()
379 priv->phycr1); in rtl8211f_config_init()
386 switch (phydev->interface) { in rtl8211f_config_init()
407 default: /* the rest of the modes imply leaving delay as is. */ in rtl8211f_config_init()
414 dev_err(dev, "Failed to update the TX delay register\n"); in rtl8211f_config_init()
418 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", in rtl8211f_config_init()
422 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", in rtl8211f_config_init()
429 dev_err(dev, "Failed to update the RX delay register\n"); in rtl8211f_config_init()
433 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", in rtl8211f_config_init()
437 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", in rtl8211f_config_init()
441 if (priv->has_phycr2) { in rtl8211f_config_init()
443 RTL8211F_CLKOUT_EN, priv->phycr2); in rtl8211f_config_init()
458 struct rtl821x_priv *priv = phydev->priv; in rtl821x_suspend()
461 if (!phydev->wol_enabled) { in rtl821x_suspend()
467 clk_disable_unprepare(priv->clk); in rtl821x_suspend()
475 struct rtl821x_priv *priv = phydev->priv; in rtl821x_resume()
478 if (!phydev->wol_enabled) in rtl821x_resume()
479 clk_prepare_enable(priv->clk); in rtl821x_resume()
500 * - Link: Configurable subset of 10/100/1000 link rates in rtl8211f_led_hw_is_supported()
501 * - Active: Blink on activity, RX or TX is not differentiated in rtl8211f_led_hw_is_supported()
503 * - A: Link and Active indication at configurable, but matching, in rtl8211f_led_hw_is_supported()
505 * - B: Link indication at configurable subset of 10/100/1000 link in rtl8211f_led_hw_is_supported()
512 return -EINVAL; in rtl8211f_led_hw_is_supported()
516 return -EOPNOTSUPP; in rtl8211f_led_hw_is_supported()
518 /* RX and TX are not differentiated, either both are set or not set. */ in rtl8211f_led_hw_is_supported()
520 return -EOPNOTSUPP; in rtl8211f_led_hw_is_supported()
531 return -EINVAL; in rtl8211f_led_hw_control_get()
564 return -EINVAL; in rtl8211f_led_hw_control_set()
591 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ in rtl8211e_config_init()
592 switch (phydev->interface) { in rtl8211e_config_init()
609 /* According to a sample driver there is a 0x1c config register on the in rtl8211e_config_init()
611 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. in rtl8211e_config_init()
614 * 13 = Force Tx RX Delay controlled by bit12 bit11, in rtl8211e_config_init()
615 * 12 = RX Delay, 11 = TX Delay in rtl8211e_config_init()
655 dev_err(&phydev->mdio.dev, in rtl8366rb_config_init()
667 phydev->speed = SPEED_10; in rtlgen_decode_speed()
670 phydev->speed = SPEED_100; in rtlgen_decode_speed()
673 phydev->speed = SPEED_1000; in rtlgen_decode_speed()
676 phydev->speed = SPEED_10000; in rtlgen_decode_speed()
679 phydev->speed = SPEED_2500; in rtlgen_decode_speed()
682 phydev->speed = SPEED_5000; in rtlgen_decode_speed()
697 if (!phydev->link) in rtlgen_read_status()
726 ret = -EOPNOTSUPP; in rtlgen_read_mmd()
742 ret = -EOPNOTSUPP; in rtlgen_write_mmd()
752 if (ret != -EOPNOTSUPP) in rtl822x_read_mmd()
777 if (ret != -EOPNOTSUPP) in rtl822x_write_mmd()
796 phydev->host_interfaces) || in rtl822xb_config_init()
797 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; in rtl822xb_config_init()
800 phydev->host_interfaces) || in rtl822xb_config_init()
801 phydev->interface == PHY_INTERFACE_MODE_SGMII; in rtl822xb_config_init()
804 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, in rtl822xb_config_init()
806 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, in rtl822xb_config_init()
815 phydev->rate_matching = RATE_MATCH_PAUSE; in rtl822xb_config_init()
818 phydev->rate_matching = RATE_MATCH_NONE; in rtl822xb_config_init()
851 /* Only rate matching at 2500base-x */ in rtl822xb_get_rate_matching()
876 phydev->supported, val & MDIO_PMA_SPEED_2_5G); in rtl822x_get_features()
878 phydev->supported, val & MDIO_PMA_SPEED_5G); in rtl822x_get_features()
880 phydev->supported, val & MDIO_SPEED_10G); in rtl822x_get_features()
889 if (phydev->autoneg == AUTONEG_ENABLE) { in rtl822x_config_aneg()
890 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); in rtl822x_config_aneg()
907 if (!phydev->link) in rtl822xb_update_interface()
917 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; in rtl822xb_update_interface()
920 phydev->interface = PHY_INTERFACE_MODE_SGMII; in rtl822xb_update_interface()
927 if (phydev->autoneg == AUTONEG_ENABLE) { in rtl822x_read_status()
933 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, in rtl822x_read_status()
956 phydev->supported); in rtl822x_c45_get_features()
966 if (phydev->autoneg == AUTONEG_DISABLE) in rtl822x_c45_config_aneg()
975 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); in rtl822x_c45_config_aneg()
997 if (phydev->autoneg == AUTONEG_ENABLE) { in rtl822x_c45_read_status()
1003 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); in rtl822x_c45_read_status()
1006 if (!phydev->link) in rtl822x_c45_read_status()
1045 return phydev->phy_id == RTL_GENERIC_PHYID && in rtlgen_match_phy_device()
1051 return phydev->phy_id == RTL_GENERIC_PHYID && in rtl8226_match_phy_device()
1058 if (phydev->is_c45) in rtlgen_is_c45_match()
1059 return is_c45 && (id == phydev->c45_ids.device_ids[1]); in rtlgen_is_c45_match()
1061 return !is_c45 && (id == phydev->phy_id); in rtlgen_is_c45_match()
1115 phydev->autoneg = AUTONEG_DISABLE; in rtl9000a_config_init()
1116 phydev->speed = SPEED_100; in rtl9000a_config_init()
1117 phydev->duplex = DUPLEX_FULL; in rtl9000a_config_init()
1127 switch (phydev->master_slave_set) { in rtl9000a_config_aneg()
1138 return -EOPNOTSUPP; in rtl9000a_config_aneg()
1152 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in rtl9000a_read_status()
1153 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in rtl9000a_read_status()
1163 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in rtl9000a_read_status()
1165 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in rtl9000a_read_status()
1171 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in rtl9000a_read_status()
1173 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in rtl9000a_read_status()
1192 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl9000a_config_intr()
1317 .name = "RTL8211F-VD Gigabit Ethernet",
1329 .name = "Generic FE-GE Realtek PHY",
1366 .name = "RTL8226-CG 2.5Gbps PHY",
1376 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1388 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1400 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1410 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1422 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
1442 .name = "RTL8126A-internal 5Gbps PHY",
1488 .name = "RTL8365MB-VC Gigabit Ethernet",