| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | micrel.txt | 7 - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs.
9 Configure the LED mode with single value. The list of PHYs and the
21 See the respective PHY datasheet for the mode values.
23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
30 non-standard, inverted function of this configuration bit.
31 Specifically, a clock reference ("rmii-ref" below) is always needed to
32 actually select a mode.
[all …]
|
| D | ti,dp83822.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
14 The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
16 data over standard, twisted-pair cables or to connect to an external,
17 fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
18 connect to a MAC through a standard MII, RMII, or RGMII interface
24 - $ref: ethernet-phy.yaml#
30 ti,link-loss-low:
[all …]
|
| D | mediatek-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
[all …]
|
| D | nxp,tja11xx.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
23 - ethernet-phy-id0180.dd00
[all …]
|
| D | actions,owl-emac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/actions,owl-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
14 It provides the RMII and SMII interfaces and is compliant with the
15 IEEE 802.3 CSMA/CD standard, supporting both half-duplex and full-duplex
19 - $ref: ethernet-controller.yaml#
24 - const: actions,owl-emac
25 - items:
[all …]
|
| D | faraday,ftgmac100.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: ethernet-controller.yaml#
13 - Po-Yu Chuang <ratbert@faraday-tech.com>
18 - const: faraday,ftgmac100
19 - items:
20 - enum:
21 - aspeed,ast2400-mac
22 - aspeed,ast2500-mac
[all …]
|
| D | mediatek,star-emac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
14 It's compliant with 802.3 standards and supports half- and full-duplex
15 modes with flow-control as well as CRC offloading and VLAN tags.
18 - $ref: ethernet-controller.yaml#
23 - mediatek,mt8516-eth
24 - mediatek,mt8518-eth
[all …]
|
| D | cpsw-phy-sel.txt | 1 TI CPSW Phy mode Selection Device Tree Bindings (DEPRECATED)
2 -----------------------------------------------
5 - compatible : Should be "ti,am3352-cpsw-phy-sel" for am335x platform and
6 "ti,dra7xx-cpsw-phy-sel" for dra7xx platform
7 "ti,am43xx-cpsw-phy-sel" for am43xx platform
8 - reg : physical base address and size of the cpsw
10 - reg-names : names of the register map given in "reg" node
13 -rmii-clock-ext : If present, the driver will configure the RMII
18 phy_sel: cpsw-phy-sel@44e10650 {
19 compatible = "ti,am3352-cpsw-phy-sel";
[all …]
|
| D | lpc-eth.txt | 4 - compatible: Should be "nxp,lpc-eth"
5 - reg: Address and length of the register set for the device
6 - interrupts: Should contain ethernet controller interrupt
9 - phy-mode: See ethernet.txt file in the same directory. If the property is
10 absent, "rmii" is assumed.
11 - use-iram: Use LPC32xx internal SRAM (IRAM) for DMA buffering
14 - mdio : specifies the mdio bus, used as a container for phy nodes according to
21 compatible = "nxp,lpc-eth";
23 interrupt-parent = <&mic>;
26 phy-mode = "rmii";
[all …]
|
| D | adi,adin.yaml | 1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
[all …]
|
| D | loongson,ls1c-emac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/loongson,ls1c-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1C Ethernet MAC Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 Loongson-1C Ethernet MAC Controller is based on
17 - 10/100Mbps
18 - Full-duplex operation (IEEE 802.3x flow control automatic transmission)
19 - Half-duplex operation (CSMA/CD Protocol and back-pressure support)
[all …]
|
| D | sunplus,sp7021-emac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/sunplus,sp7021-emac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Wells Lu <wellslutw@gmail.com>
19 const: sunplus,sp7021-emac
33 ethernet-ports:
39 "#address-cells":
42 "#size-cells":
46 "^port@[0-1]$":
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/net/dsa/ |
| D | microchip,ksz.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Vasut <marex@denx.de>
11 - Woojung Huh <Woojung.Huh@microchip.com>
14 - $ref: /schemas/spi/spi-peripheral-props.yaml#
21 - microchip,ksz8765
22 - microchip,ksz8794
23 - microchip,ksz8795
24 - microchip,ksz8863
[all …]
|
| D | lan9303.txt | 2 -------------------------------------------------
6 - compatible: should be
7 - "smsc,lan9303-i2c" for I2C managed mode
9 - "smsc,lan9303-mdio" for mdio managed mode
13 - reset-gpios: GPIO to be used to reset the whole device
14 - reset-duration: reset duration in milliseconds, defaults to 200 ms
23 auto-detected and mapped accordingly.
27 I2C managed mode:
31 fixed-link { /* RMII fixed link to LAN9303 */
33 full-duplex;
[all …]
|
| /linux-6.12.1/arch/arm/boot/dts/nxp/imx/ |
| D | imx6ul-kontron-sl-common.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
12 stdout-path = &uart4;
22 cs-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_ecspi2>;
28 compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
29 spi-max-frequency = <50000000>;
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
[all …]
|
| D | imx6ull-seeed-npi-dev-board.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/gpio/gpio.h>
11 stdout-path = &uart1;
14 gpio_buttons: gpio-keys {
15 compatible = "gpio-keys";
16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_button>;
19 button-0 {
23 wakeup-source;
27 gpio-leds {
[all …]
|
| D | imx6qp-prtwd3.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
16 stdout-path = &uart4;
29 clock_ksz8081: clock-ksz8081 {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <50000000>;
35 clock_ksz9031: clock-ksz9031 {
36 compatible = "fixed-clock";
[all …]
|
| /linux-6.12.1/arch/arm/boot/dts/microchip/ |
| D | at91sam9x25ek.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9x25ek.dts - Device Tree file for AT91SAM9X25-EK board
8 /dts-v1/;
13 model = "Atmel AT91SAM9X25-EK";
22 phy-mode = "rmii";
27 phy-mode = "rmii";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_pwm0_pwm0_1>;
|
| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | ti,phy-gmii-sel.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: CPSW Port's Interface Mode Selection PHY
11 - Kishon Vijay Abraham I <kishon@ti.com>
15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
16 The interface mode is selected by configuring the MII mode selection register(s)
20 +--------------+
[all …]
|
| /linux-6.12.1/arch/arm/boot/dts/st/ |
| D | stm32mp151a-prtt1c.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
8 #include "stm32mp151a-prtt1l.dtsi"
14 clock_ksz9031: clock-ksz9031 {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <25000000>;
20 clock_sja1105: clock-sja1105 {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
[all …]
|
| D | stm32mp151c-mect1s.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
10 #include "stm32mp15-pinctrl.dtsi"
11 #include "stm32mp15xxaa-pinctrl.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
14 #include <dt-bindings/leds/common.h>
21 stdout-path = "serial0:1500000n8";
33 v3v3: regulator-v3v3 {
34 compatible = "regulator-fixed";
[all …]
|
| /linux-6.12.1/Documentation/networking/dsa/ |
| D | sja1105.rst | 8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
18 - SJA1110B: Third generation, TTEthernet, SGMII, 100base-T1, 100base-TX
[all …]
|
| /linux-6.12.1/drivers/net/ethernet/arc/ |
| D | emac_rockchip.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * emac-rockchip.c - Rockchip EMAC specific glue layer
39 u32 speed_offset = emac->soc_data->grf_speed_offset; in emac_rockchip_set_mac_speed()
55 err = regmap_write(emac->grf, emac->soc_data->grf_offset, data); in emac_rockchip_set_mac_speed()
77 .compatible = "rockchip,rk3036-emac",
81 .compatible = "rockchip,rk3066-emac",
85 .compatible = "rockchip,rk3188-emac",
95 struct device *dev = &pdev->dev; in emac_rockchip_probe()
103 if (!pdev->dev.of_node) in emac_rockchip_probe()
104 return -ENODEV; in emac_rockchip_probe()
[all …]
|
| /linux-6.12.1/drivers/net/ethernet/ti/ |
| D | cpsw-phy-sel.c | 1 // SPDX-License-Identifier: GPL-2.0
44 u32 mode = 0; in cpsw_gmii_sel_am3352() local
47 reg = readl(priv->gmii_sel); in cpsw_gmii_sel_am3352()
51 mode = AM33XX_GMII_SEL_MODE_RMII; in cpsw_gmii_sel_am3352()
55 mode = AM33XX_GMII_SEL_MODE_RGMII; in cpsw_gmii_sel_am3352()
61 mode = AM33XX_GMII_SEL_MODE_RGMII; in cpsw_gmii_sel_am3352()
66 dev_warn(priv->dev, in cpsw_gmii_sel_am3352()
67 "Unsupported PHY mode: \"%s\". Defaulting to MII.\n", in cpsw_gmii_sel_am3352()
71 mode = AM33XX_GMII_SEL_MODE_MII; in cpsw_gmii_sel_am3352()
77 mode <<= slave * 2; in cpsw_gmii_sel_am3352()
[all …]
|
| /linux-6.12.1/arch/arm/boot/dts/ti/omap/ |
| D | am335x-icev2.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2016 Texas Instruments Incorporated - https://www.ti.com/
11 /dts-v1/;
16 model = "TI AM3359 ICE-V2";
17 compatible = "ti,am3359-icev2", "ti,am33xx";
25 stdout-path = &uart3;
29 compatible = "regulator-fixed";
30 regulator-name = "vbat";
31 regulator-min-microvolt = <5000000>;
32 regulator-max-microvolt = <5000000>;
[all …]
|