Lines Matching +full:rmii +full:- +full:mode
1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
23 - ethernet-phy-id0180.dd00
24 - ethernet-phy-id0180.dd01
25 - ethernet-phy-id0180.dd02
26 - ethernet-phy-id0180.dc80
27 - ethernet-phy-id0180.dc82
28 - ethernet-phy-id001b.b010
29 - ethernet-phy-id001b.b013
30 - ethernet-phy-id001b.b030
31 - ethernet-phy-id001b.b031
34 - $ref: ethernet-phy.yaml#
35 - if:
40 - ethernet-phy-id0180.dc40
41 - ethernet-phy-id0180.dc41
42 - ethernet-phy-id0180.dc48
43 - ethernet-phy-id0180.dd00
44 - ethernet-phy-id0180.dd01
45 - ethernet-phy-id0180.dd02
49 nxp,rmii-refclk-in:
53 in RMII mode. This clock signal is provided by the PHY and is
60 interface reference clock input when RMII mode enabled.
62 reference clock output when RMII mode enabled.
66 "^ethernet-phy@[0-9a-f]+$":
81 - reg
86 - |
88 #address-cells = <1>;
89 #size-cells = <0>;
91 tja1101_phy0: ethernet-phy@4 {
92 compatible = "ethernet-phy-id0180.dc40";
94 nxp,rmii-refclk-in;
97 - |
99 #address-cells = <1>;
100 #size-cells = <0>;
102 tja1102_phy0: ethernet-phy@4 {
104 #address-cells = <1>;
105 #size-cells = <0>;
107 tja1102_phy1: ethernet-phy@5 {