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/linux-6.12.1/Documentation/devicetree/bindings/rtc/
Dmarvell,pxa-rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/rtc/marvell,pxa-rtc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: PXA Real Time Clock
10 - Javier Carrasco <javier.carrasco.cruz@gmail.com>
13 - $ref: rtc.yaml#
17 const: marvell,pxa-rtc
24 - description: 1 Hz
25 - description: Alarm
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/linux-6.12.1/drivers/rtc/
Drtc-pxa.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/rtc.h>
18 #include "rtc-sa1100.h"
20 #define RTC_DEF_DIVIDER (32768 - 1)
25 * PXA Registers and bits definitions
30 #define RTSR_SWALE2 (1 << 11) /* RTC stopwatch alarm2 enable */
31 #define RTSR_SWAL2 (1 << 10) /* RTC stopwatch alarm2 detected */
32 #define RTSR_SWALE1 (1 << 9) /* RTC stopwatch alarm1 enable */
33 #define RTSR_SWAL1 (1 << 8) /* RTC stopwatch alarm1 detected */
34 #define RTSR_RDALE2 (1 << 7) /* RTC alarm2 enable */
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Drtc-vt8500.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/rtc/rtc-vt8500.c
7 * Based on rtc-pxa.c
11 #include <linux/rtc.h>
64 #define VT8500_RTC_CR_ENABLE (1 << 0) /* Enable RTC */
75 struct rtc_device *rtc; member
85 spin_lock(&vt8500_rtc->lock); in vt8500_rtc_irq()
88 isr = readl(vt8500_rtc->regbase + VT8500_RTC_IS); in vt8500_rtc_irq()
89 writel(isr, vt8500_rtc->regbase + VT8500_RTC_IS); in vt8500_rtc_irq()
91 spin_unlock(&vt8500_rtc->lock); in vt8500_rtc_irq()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
3 # Makefile for RTC class/drivers.
6 ccflags-$(CONFIG_RTC_DEBUG) := -DDEBUG
8 obj-$(CONFIG_RTC_LIB) += lib.o
9 obj-$(CONFIG_RTC_CLASS) += rtc-core.o
10 obj-$(CONFIG_RTC_MC146818_LIB) += rtc-mc146818-lib.o
11 rtc-core-y := class.o interface.o
13 rtc-core-$(CONFIG_RTC_NVMEM) += nvmem.o
14 rtc-core-$(CONFIG_RTC_INTF_DEV) += dev.o
15 rtc-core-$(CONFIG_RTC_INTF_PROC) += proc.o
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DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # RTC class/drivers configuration
19 Generic RTC class support. If you say yes here, you will
26 bool "Set system time from RTC on startup and resume"
30 the value read from a specified RTC device. This is useful to avoid
34 string "RTC used to set the system time"
38 The RTC device that will be used to (re)initialize the system
44 This clock should be battery-backed, so that it reads the correct
45 time when the system boots from a power-off state. Otherwise, your
50 sleep states. Do not specify an RTC here unless it stays powered
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/linux-6.12.1/arch/arm/boot/dts/intel/pxa/
Dpxa2xx.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * pxa2xx.dtsi - Device Tree Include file for Marvell PXA2xx family SoC
8 #include "dt-bindings/clock/pxa-clock.h"
12 mux- ## func { \
17 mux- ## func { \
20 low-power-disable; \
23 mux- ## func { \
26 low-power-enable; \
30 #address-cells = <1>;
31 #size-cells = <1>;
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Dpxa27x.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include "dt-bindings/clock/pxa-clock.h"
11 pdma: dma-controller@40000000 {
12 compatible = "marvell,pdma-1.0";
15 #dma-cells = <2>;
17 #dma-channels = <32>;
18 dma-channels = <32>;
19 #dma-requests = <75>;
20 dma-requests = <75>;
24 pxairq: interrupt-controller@40d00000 {
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Dpxa25x.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include "dt-bindings/clock/pxa-clock.h"
17 #address-cells = <1>;
18 #size-cells = <1>;
22 compatible = "marvell,pxa250-core-clocks";
23 #clock-cells = <1>;
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <3686400>;
32 clock-output-names = "ostimer";
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/linux-6.12.1/arch/arm/mach-pxa/
Ddevices.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
8 #include <linux/dma-mapping.h>
10 #include <linux/gpio-pxa.h>
11 #include <linux/platform_data/i2c-pxa.h>
12 #include <linux/soc/pxa/cpu.h>
15 #include <linux/platform_data/video-pxafb.h>
16 #include <linux/platform_data/mmc-pxamci.h>
18 #include <linux/platform_data/usb-ohci-pxa27x.h>
21 #include "mfp-pxa2xx.h"
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Dregs-rtc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include "pxa-regs.h"
11 #define RCNR __REG(0x40900000) /* RTC Count Register */
12 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
13 #define RTSR __REG(0x40900008) /* RTC Status Register */
14 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
20 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
21 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
22 #define RTSR_AL (1 << 0) /* RTC alarm detected */
Dpxa25x.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-pxa/pxa25x.c
13 * initialization stuff for PXA machines which can be overridden later if
17 #include <linux/dma/pxa-dma.h>
19 #include <linux/gpio-pxa.h>
29 #include <linux/soc/pxa/cpu.h>
30 #include <linux/soc/pxa/smemc.h>
38 #include "addr-map.h"
54 * List of global PXA peripheral registers to preserve.
117 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
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Dpxa2xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-pxa/include/mach/pxa2xx-regs.h
5 * Taken from pxa-regs.h by Russell King
14 #include "pxa-regs.h"
23 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
24 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
25 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
28 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
29 #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
30 #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
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Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-pxa/include/mach/pxa3xx-regs.h
13 #include "pxa-regs.h"
30 #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
31 #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
33 #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
42 #define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */
43 #define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */
44 #define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */
45 #define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */
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Dirqs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * arch/arm/mach-pxa/include/mach/irqs.h
20 #define IRQ_USBH1 PXA_IRQ(3) /* USB Host interrupt 2 (non-OHCI,PXA27x) */
23 #define IRQ_ACIPC0 PXA_IRQ(5) /* AP-CP Communication (PXA930) */
26 #define IRQ_OST_4_11 PXA_IRQ(7) /* OS timer 4-11 matches (PXA27x) */
29 #define IRQ_GPIO_2_x PXA_IRQ(10) /* GPIO[2-x] Edge Detect */
42 #define IRQ_ACIPC2 PXA_IRQ(19) /* AP-CP Communication (PXA930) */
53 #define IRQ_RTC1Hz PXA_IRQ(30) /* RTC HZ Clock Tick */
54 #define IRQ_RTCAlrm PXA_IRQ(31) /* RTC Alarm */
64 #define IRQ_ACIPC1 PXA_IRQ(40) /* AP-CP Communication (PXA930) */
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/linux-6.12.1/drivers/clk/pxa/
Dclk-pxa27x.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Heavily inspired from former arch/arm/mach-pxa/clock.c.
9 #include <linux/clk-provider.h>
14 #include <linux/soc/pxa/smemc.h>
15 #include <linux/clk/pxa.h>
17 #include <dt-bindings/clock/pxa-clock.h>
18 #include "clk-pxa.h"
19 #include "clk-pxa2xx.h"
67 return (interval - 31) / 32; in mdrefr_dri()
132 PXA27X_PBUS_CKEN("pxa2xx-uart.0", NULL, FFUART, 2, 42, 1),
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Dclk-pxa25x.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Heavily inspired from former arch/arm/mach-pxa/pxa25x.c.
9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
12 #include <linux/clk-provider.h>
14 #include <linux/clk/pxa.h>
18 #include <linux/soc/pxa/smemc.h>
19 #include <linux/soc/pxa/cpu.h>
21 #include <dt-bindings/clock/pxa-clock.h>
22 #include "clk-pxa.h"
23 #include "clk-pxa2xx.h"
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Dclk-pxa3xx.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Heavily inspired from former arch/arm/mach-pxa/pxa3xx.c
9 * For non-devicetree platforms. Once pxa is fully converted to devicetree, this
14 #include <linux/clk-provider.h>
17 #include <linux/soc/pxa/cpu.h>
18 #include <linux/soc/pxa/smemc.h>
19 #include <linux/clk/pxa.h>
21 #include <dt-bindings/clock/pxa-clock.h>
22 #include "clk-pxa.h"
44 #define ACCR_HSS_MASK (0x3 << 14) /* System Bus-Clock Frequency Select */
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/linux-6.12.1/drivers/clocksource/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
190 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
213 32-bit free running decrementing counters.
248 bool "Integrator-AP timer driver" if COMPILE_TEST
251 Enables support for the Integrator-AP timer.
276 available on many OMAP-like platforms.
295 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
299 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
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/linux-6.12.1/arch/arm/mach-sa1100/
Dgeneric.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/generic.c
15 #include <linux/dma-mapping.h>
23 #include <linux/irqchip/irq-sa11x0.h>
40 #include <clocksource/pxa.h>
75 * Default power-off for SA1100
83 /* enable wake-up on GPIO0 (Assabet...) */ in sa1100_power_off()
102 /* Use on-chip reset capability */ in sa11x0_restart()
110 dev->dev.platform_data = data; in sa11x0_register_device()
114 dev->name, err); in sa11x0_register_device()
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/linux-6.12.1/drivers/mfd/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
57 tristate "Active-semi ACT8945A"
62 Support for the ACT8945A PMIC from Active-semi. This device
63 features three step-down DC/DC converters and four low-dropout
79 sun4i-gpadc-iio and the hwmon driver iio_hwmon.
82 called sun4i-gpadc.
113 tablets etc. It has 4 DC/DC step-down regulators, 3 DC/DC step-down
114 controllers, 11 LDOs, RTC, automatic battery, temperature and
144 over at91-usart-serial driver and usart-spi-driver. Only one function
160 tristate "Atmel HLCDC (High-end LCD Controller)"
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/linux-6.12.1/
DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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DCREDITS1 This is at least a partial credits-file of people that have
4 scripts. The fields are: name (N), email (E), web-address
6 snail-mail address (S).
10 ----------
47 D: in-kernel DRM Maintainer
72 E: tim_alpaerts@toyota-motor-europe.com
76 S: B-2610 Wilrijk-Antwerpen
81 W: http://www-stu.christs.cam.ac.uk/~aia21/
102 D: Maintainer of ide-cd and Uniform CD-ROM driver,
103 D: ATAPI CD-Changer support, Major 2.1.x CD-ROM update.
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