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/linux-6.12.1/drivers/net/ethernet/mellanox/mlxsw/
Dspectrum_port_range.c26 const struct mlxsw_sp_port_range_reg *prr) in mlxsw_sp_port_range_reg_configure() argument
33 mlxsw_reg_pprr_pack(pprr_pl, prr->index); in mlxsw_sp_port_range_reg_configure()
36 mlxsw_reg_pprr_src_set(pprr_pl, prr->range.source); in mlxsw_sp_port_range_reg_configure()
37 mlxsw_reg_pprr_dst_set(pprr_pl, !prr->range.source); in mlxsw_sp_port_range_reg_configure()
40 mlxsw_reg_pprr_port_range_min_set(pprr_pl, prr->range.min); in mlxsw_sp_port_range_reg_configure()
41 mlxsw_reg_pprr_port_range_max_set(pprr_pl, prr->range.max); in mlxsw_sp_port_range_reg_configure()
52 struct mlxsw_sp_port_range_reg *prr; in mlxsw_sp_port_range_reg_create() local
55 prr = kzalloc(sizeof(*prr), GFP_KERNEL); in mlxsw_sp_port_range_reg_create()
56 if (!prr) in mlxsw_sp_port_range_reg_create()
59 prr->range = *range; in mlxsw_sp_port_range_reg_create()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/hwinfo/
Drenesas,prr.yaml4 $id: http://devicetree.org/schemas/hwinfo/renesas,prr.yaml#
21 - renesas,prr
34 prr: chipid@ff000044 {
35 compatible = "renesas,prr";
/linux-6.12.1/Documentation/devicetree/bindings/fpga/
Dfpga-region.yaml46 Partial Reconfiguration Region (PRR)
48 * A PRR is a specific section of an FPGA reserved for reconfiguration.
49 * A base (or static) FPGA image may create a set of PRR's that later may
51 * The size and specific location of each PRR is fixed.
52 * The connections at the edge of each PRR are fixed. The image that is loaded
53 into a PRR must fit and must use a subset of the region's connections.
59 * An FPGA image that is designed to be loaded into a PRR. There may be
60 any number of personas designed to fit into a PRR, but only one at a time
108 a soft logic bridge (Bridge0-2) in the FPGA. The contents of each PRR can be
159 base FPGA region. The "Full Reconfiguration to add PRR's" example below shows
[all …]
/linux-6.12.1/arch/sh/kernel/cpu/sh4/
Dprobe.c17 unsigned long pvr, prr, cvr; in cpu_probe() local
29 prr = (__raw_readl(CCN_PRR) >> 4) & 0xff; in cpu_probe()
106 if (prr == 0x61) in cpu_probe()
108 else if (prr == 0xa1) in cpu_probe()
129 switch (prr) { in cpu_probe()
145 switch (prr) { in cpu_probe()
180 switch (prr) { in cpu_probe()
/linux-6.12.1/drivers/soc/renesas/
Drenesas-soc.c17 u32 reg; /* CCCR or PRR, if not in DT */
22 .reg = 0xff000044, /* PRR (Product Register) */
27 .reg = 0xff000044, /* PRR (Product Register) */
32 .reg = 0xfff00044, /* PRR (Product Register) */
58 .reg = 0xff000044, /* PRR (Product Register) */
63 .reg = 0xfff00044, /* PRR (Product Register) */
470 { .compatible = "renesas,prr", .data = &id_prr },
503 /* Try hardcoded CCCR/PRR fallback */ in renesas_soc_init()
/linux-6.12.1/Documentation/spi/
Dbutterfly.rst43 (a) flash new firmware that disables SPI (set PRR.2, and disable pullups
/linux-6.12.1/arch/arm/boot/dts/renesas/
Dr8a7779.dtsi714 prr: chipid@ff000044 { label
715 compatible = "renesas,prr";
Dr8a73a4.dtsi762 prr: chipid@ff000044 { label
763 compatible = "renesas,prr";
Dr8a7792.dtsi947 prr: chipid@ff000044 { label
948 compatible = "renesas,prr";
Dr8a77470.dtsi1020 prr: chipid@ff000044 { label
1021 compatible = "renesas,prr";
Dr8a7794.dtsi1441 prr: chipid@ff000044 { label
1442 compatible = "renesas,prr";
Dr8a7793.dtsi1455 prr: chipid@ff000044 { label
1456 compatible = "renesas,prr";
Dr8a7745.dtsi1595 prr: chipid@ff000044 { label
1596 compatible = "renesas,prr";
Dr8a7744.dtsi1771 prr: chipid@ff000044 { label
1772 compatible = "renesas,prr";
Dr8a7743.dtsi1785 prr: chipid@ff000044 { label
1786 compatible = "renesas,prr";
Dr8a7742.dtsi1878 prr: chipid@ff000044 { label
1879 compatible = "renesas,prr";
Dr8a7791.dtsi1876 prr: chipid@ff000044 { label
1877 compatible = "renesas,prr";
Dr8a7790.dtsi1950 prr: chipid@ff000044 { label
1951 compatible = "renesas,prr";
/linux-6.12.1/arch/sh/mm/
Dcache-sh4.c385 printk("PVR=%08x CVR=%08x PRR=%08x\n", in sh4_cache_init()
/linux-6.12.1/arch/arm64/boot/dts/renesas/
Dr8a77970.dtsi1196 prr: chipid@fff00044 { label
1197 compatible = "renesas,prr";
Dr8a779f0.dtsi1272 prr: chipid@fff00044 { label
1273 compatible = "renesas,prr";
Dr8a77995.dtsi1448 prr: chipid@fff00044 { label
1449 compatible = "renesas,prr";
Dr8a77980.dtsi1579 prr: chipid@fff00044 { label
1580 compatible = "renesas,prr";
Dr8a779h0.dtsi1999 prr: chipid@fff00044 { label
2000 compatible = "renesas,prr";
Dr8a774c0.dtsi1953 prr: chipid@fff00044 { label
1954 compatible = "renesas,prr";

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