Searched +full:ports +full:- +full:implemented (Results 1 – 25 of 277) sorted by relevance
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| /linux-6.12.1/Documentation/devicetree/bindings/soundwire/ |
| D | qcom,soundwire.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
19 - qcom,soundwire-v1.3.0
20 - qcom,soundwire-v1.5.0
21 - qcom,soundwire-v1.5.1
22 - qcom,soundwire-v1.6.0
23 - qcom,soundwire-v1.7.0
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| /linux-6.12.1/Documentation/networking/dsa/ |
| D | lan9303.rst | 6 the two external ethernet ports. The third port is an RMII/MII interface to a
13 The driver is implemented as a DSA driver, see ``Documentation/networking/dsa/dsa.rst``.
24 When both user ports are joined to the same bridge, the normal HW MAC learning
29 If one of the user ports leave the bridge, the ports goes back to the initial
36 - Support for VLAN filtering is not implemented
37 - The HW does not support VLAN-specific fdb entries
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| D | dsa.rst | 22 An Ethernet switch typically comprises multiple front-panel ports and one
23 or more CPU or management ports. The DSA subsystem currently relies on the
27 gateways, or even top-of-rack switches. This host Ethernet controller will
33 ports are referred to as "dsa" ports in DSA terminology and code. A collection
36 For each front-panel port, DSA creates specialized network devices which are
37 used as controlling and data-flowing endpoints for use by the Linux networking
43 Ethernet frame it receives to/from specific ports to help the management
46 - what port is this frame coming from
47 - what was the reason why this frame got forwarded
48 - how to send CPU originated traffic to specific ports
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| D | bcm_sf2.rst | 8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
22 fail-over not to lose packets during a MoCA role re-election, as well as out of
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| D | b53.rst | 1 .. SPDX-License-Identifier: GPL-2.0
16 The driver is located in ``drivers/net/dsa/b53/`` and is implemented as a
20 The switch is, if possible, configured to enable a Broadcom specific 4-bytes
30 configuration described in the :ref:`dsa-config-showcases`.
33 ----------------------------------
38 See :ref:`dsa-tagged-configuration`.
41 -------------------------------------
48 The configuration slightly differ from the :ref:`dsa-vlan-configuration`.
54 In difference to the configuration described in :ref:`dsa-vlan-configuration`
64 .. code-block:: sh
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| /linux-6.12.1/Documentation/devicetree/bindings/ata/ |
| D | rockchip,dwc-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
25 - compatible
30 - enum:
31 - rockchip,rk3568-dwc-ahci
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| D | baikal,bt1-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
21 const: baikal,bt1-ahci
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| D | ahci-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
32 reg-names:
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| D | mediatek,mtk-ahci.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ata/mediatek,mtk-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ryder Lee <ryder.lee@mediatek.com>
13 - $ref: ahci-common.yaml#
18 - enum:
19 - mediatek,mt7622-ahci
20 - const: mediatek,mtk-ahci
28 interrupt-names:
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| /linux-6.12.1/Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
42 implemented by the SoC. Each GPIO is assigned to a port, and a port may
47 The number of ports implemented by each GPIO controller varies. The number
48 of implemented GPIOs within each port varies. GPIO registers within a
53 controller, are both extremely non-linear. The header file
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| /linux-6.12.1/drivers/scsi/mvsas/ |
| D | mv_64xx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
21 MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
24 MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
53 /* ports 1-3 follow after this */
56 /* ports 5-7 follow after this */
60 /* ports 1-3 follow after this */
62 /* ports 5-7 follow after this */
68 /* ports 1-3 follow after this */
71 /* ports 5-7 follow after this */
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| D | mv_94xx.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
32 MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
35 MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */
66 MVS_NON_NCQ_ERR_0 = 0x168, /* SRS Non-specific NCQ Error */
72 /* ports 1-3 follow after this */
75 /* ports 5-7 follow after this */
79 /* ports 1-3 follow after this */
81 /* ports 5-7 follow after this */
84 /* ports 1-3 follow after this */
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| /linux-6.12.1/Documentation/networking/devlink/ |
| D | netdevsim.rst | 1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 * - ``max_macs``
18 - driverinit
20 The ``netdevsim`` driver also implements the following driver-specific
23 .. list-table:: Driver-specific parameters implemented
26 * - Name
27 - Type
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| D | mlx5.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 This document describes the devlink features implemented by the ``mlx5``
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 - Validation
18 * - ``enable_roce``
19 - driverinit
20 - Type: Boolean
26 * - ``io_eq_size``
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| /linux-6.12.1/Documentation/devicetree/bindings/media/ |
| D | cdns,csi2tx.txt | 1 Cadence MIPI-CSI2 TX controller
4 The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
8 - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
9 for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
10 - reg: base address and size of the memory mapped region
11 - clocks: phandles to the clocks driving the controller
12 - clock-names: must contain:
15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
16 implemented in hardware, between 0 and 3
19 - phys: phandle to the D-PHY. If it is set, phy-names need to be set
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| /linux-6.12.1/Documentation/hwmon/ |
| D | it87.rst | 10 Addresses scanned: from Super I/O config space (8 I/O ports)
18 Addresses scanned: from Super I/O config space (8 I/O ports)
24 Addresses scanned: from Super I/O config space (8 I/O ports)
32 Addresses scanned: from Super I/O config space (8 I/O ports)
40 Addresses scanned: from Super I/O config space (8 I/O ports)
48 Addresses scanned: from Super I/O config space (8 I/O ports)
56 Addresses scanned: from Super I/O config space (8 I/O ports)
64 Addresses scanned: from Super I/O config space (8 I/O ports)
72 Addresses scanned: from Super I/O config space (8 I/O ports)
80 Addresses scanned: from Super I/O config space (8 I/O ports)
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| D | mlxreg-fan.rst | 1 Kernel driver mlxreg-fan
6 - QMB700, equipped with 40x200GbE InfiniBand ports;
7 - MSN3700, equipped with 32x200GbE or 16x400GbE Ethernet ports;
8 - MSN3410, equipped with 6x400GbE plus 48x50GbE Ethernet ports;
9 - MSN3800, equipped with 64x1000GbE Ethernet ports;
14 board with Mellanox Quantum or Spectrume-2 devices.
15 FAN controller is implemented by the programmable device logic.
36 This setup can be re-programmed with other registers.
39 -----------
45 device. PWM and tachometers are sensed through the on-board programmable
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| /linux-6.12.1/Documentation/devicetree/bindings/soc/qcom/ |
| D | qcom,eud.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Souradeep Chowdhury <quic_schowdhu@quicinc.com>
14 mini USB-hub implemented on chip to support USB-based debug capabilities.
19 - enum:
20 - qcom,sc7280-eud
21 - const: qcom,eud
25 - description: EUD Base Register Region
26 - description: EUD Mode Manager Register
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| /linux-6.12.1/Documentation/arch/arm/sa1100/ |
| D | assabet.rst | 2 The Intel Assabet (SA-1110 evaluation) board
13 -------------------
25 -----------------------
39 John Dorsey has produced add-on patches to add support for Assabet and
55 - ftp://ftp.netwinder.org/users/n/nico/
56 - ftp://ftp.arm.linux.org.uk/pub/linux/arm/people/nico/
57 - ftp://ftp.handhelds.org/pub/linux/arm/sa-1100-patches/
59 Look for redboot-assabet*.tgz. Some installation infos are provided in
60 redboot-assabet*.txt.
64 -----------------------------
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| /linux-6.12.1/drivers/pci/ |
| D | pci-bridge-emul.c | 1 // SPDX-License-Identifier: GPL-2.0
21 #include "pci-bridge-emul.h"
28 * struct pci_bridge_reg_behavior - register bits behaviors
29 * @ro: Read-Only bits
30 * @rw: Read-Write bits
31 * @w1c: Write-1-to-Clear bits
36 * multi-bit fields) when read".
39 /* Read-only bits */
42 /* Read-write bits */
45 /* Write-1-to-clear bits */
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| /linux-6.12.1/Documentation/devicetree/bindings/arm/ |
| D | arm,coresight-dummy-sink.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/arm/arm,coresight-dummy-sink.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
19 Qualcomm platforms. It is a mini-USB hub implemented to support the USB-based
31 - Mike Leach <mike.leach@linaro.org>
32 - Suzuki K Poulose <suzuki.poulose@arm.com>
33 - James Clark <james.clark@linaro.org>
34 - Mao Jinlong <quic_jinlmao@quicinc.com>
35 - Hao Zhang <quic_hazha@quicinc.com>
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| /linux-6.12.1/Documentation/i2c/busses/ |
| D | i2c-amd8111.rst | 2 Kernel driver i2c-adm8111
6 * AMD-8111 SMBus 2.0 PCI interface
16 -----------
20 00:07.2 SMBus: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0 (rev 02)
21 Subsystem: Advanced Micro Devices [AMD] AMD-8111 SMBus 2.0
23 I/O ports at d400 [size=32]
25 in your ``lspci -v``, then this driver is for your chipset.
28 --------------------
33 -----------------
35 Supported. Both PEC and block process call support is implemented. Slave
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| /linux-6.12.1/Documentation/arch/m68k/ |
| D | buddha-driver.rst | 8 ------------------------------------------------------------------------
11 Buddha-part of the Catweasel Zorro-II version
13 The Autoconfiguration has been implemented just as Commodore
21 product number: 0 (42 for Catweasel Z-II)
23 Rom-vector: $1000
25 The card should be a Z-II board, size 64K, not for freemem
26 list, Rom-Vektor is valid, no second Autoconfig-board on the
30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
36 otherwise your chance is only 1:16 to find the board :-).
38 The local memory-map is even active when mapped to $e8:
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| /linux-6.12.1/arch/powerpc/platforms/8xx/ |
| D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
33 bool "Embedded Planet EP88xC (a.k.a. CWH-PPC-885XN-VE)"
39 MPC885 Evaluation System and/or the CWH-PPC-885XN-VE.
56 menu "Freescale Ethernet driver platform-specific options"
76 Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
77 (often 2-nd UART) will not work if this is enabled.
83 Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
84 (often 1-nd UART) will not work if this is enabled.
106 Saying Y here will cause the ports on an MPC8xx processor to be used
132 Help not implemented yet, coming soon.
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| /linux-6.12.1/Documentation/sound/designs/ |
| D | seq-oss.rst | 15 What this does - it provides the emulation of the OSS sequencer, access
53 However, each MIDI device is exclusive - that is, if a MIDI device
57 * Real-time event processing:
60 ioctl. To switch to real-time mode, send ABSTIME 0 event. The followed
61 events will be processed in real-time without queued. To switch off the
62 real-time mode, send RELTIME 0 event.
74 Run configure script with both sequencer support (``--with-sequencer=yes``)
75 and OSS emulation (``--with-oss=yes``) options. A module ``snd-seq-oss.o``
81 At beginning, this module probes all the MIDI ports which have been
83 of ports are watched by announcement mechanism of ALSA sequencer.
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