bindings/ata/mediatek%2Cmtk-ahci.yaml

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ata/mediatek,mtk-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Ryder Lee <ryder.lee@mediatek.com>
13   - $ref: ahci-common.yaml#
18       - enum:
19           - mediatek,mt7622-ahci
20       - const: mediatek,mtk-ahci
28   interrupt-names:
34   clock-names:
36       - const: ahb
37       - const: axi
38       - const: asic
39       - const: rbc
40       - const: pm
42   power-domains:
48   reset-names:
50       - const: axi
51       - const: sw
52       - const: reg
54   mediatek,phy-mode:
59   - reg
60   - interrupts
61   - interrupt-names
62   - clocks
63   - clock-names
64   - phys
65   - phy-names
66   - ports-implemented
71   - |
72     #include <dt-bindings/clock/mt7622-clk.h>
73     #include <dt-bindings/interrupt-controller/arm-gic.h>
74     #include <dt-bindings/phy/phy.h>
75     #include <dt-bindings/power/mt7622-power.h>
76     #include <dt-bindings/reset/mt7622-reset.h>
79         compatible = "mediatek,mt7622-ahci", "mediatek,mtk-ahci";
82         interrupt-names = "hostc";
88         clock-names = "ahb", "axi", "asic", "rbc", "pm";
90         phy-names = "sata-phy";
91         ports-implemented = <0x1>;
92         power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
96         reset-names = "axi", "sw", "reg";
97         mediatek,phy-mode = <&pciesys>;