| /linux-6.12.1/arch/arm/ |
| D | Kconfig.debug | 1 # SPDX-License-Identifier: GPL-2.0
44 once the kernel has booted up - it's a one time check.
104 1 - undefined instruction events
105 2 - system calls
106 4 - invalid data aborts
107 8 - SIGSEGV faults
108 16 - SIGBUS faults
112 bool "Kernel low-level debugging functions (read help!)"
125 prompt "Kernel low-level debugging port"
129 bool "Kernel low-level debugging messages via Alpine UART0"
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| /linux-6.12.1/Documentation/driver-api/serial/ |
| D | driver.rst | 2 Low Level Serial API
10 The reference implementation is contained within amba-pl011.c.
14 Low Level Serial Hardware Driver
15 --------------------------------
17 The low level serial hardware driver is responsible for supplying port
19 by uart_ops) to the core serial driver. The low level driver is also
20 responsible for handling interrupts for the port, and providing any
25 ---------------
28 the correct port structure (via uart_get_console()) and decoding command line
38 -------
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| /linux-6.12.1/drivers/gpu/drm/i915/display/ |
| D | intel_dsi_dcs_backlight.c | 50 struct intel_panel *panel = &connector->panel; in dcs_get_backlight()
53 enum port port; in dcs_get_backlight() local
54 size_t len = panel->backlight.max > U8_MAX ? 2 : 1; in dcs_get_backlight()
56 for_each_dsi_port(port, panel->vbt.dsi.bl_ports) { in dcs_get_backlight()
57 dsi_device = intel_dsi->dsi_hosts[port]->device; in dcs_get_backlight()
66 static void dcs_set_backlight(const struct drm_connector_state *conn_state, u32 level) in dcs_set_backlight() argument
68 struct intel_dsi *intel_dsi = enc_to_intel_dsi(to_intel_encoder(conn_state->best_encoder)); in dcs_set_backlight()
69 struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel; in dcs_set_backlight()
72 enum port port; in dcs_set_backlight() local
73 size_t len = panel->backlight.max > U8_MAX ? 2 : 1; in dcs_set_backlight()
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| D | intel_ddi.c | 97 int level; in intel_ddi_hdmi_level() local
99 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
100 if (level < 0) in intel_ddi_hdmi_level()
101 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
103 return level; in intel_ddi_hdmi_level()
117 * Starting with Haswell, DDI port buffers must be programmed with correct
124 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
127 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers() local
130 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
131 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
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| /linux-6.12.1/drivers/net/fddi/skfp/ |
| D | smtdef.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
22 #define OEM_USER_DATA "SK-NET FDDI V2.0 Userdata"
67 void smt_reset_defaults(struct s_smc *smc, int level);
68 static void smt_init_mib(struct s_smc *smc, int level);
74 void smt_reset_defaults(struct s_smc *smc, int level) in smt_reset_defaults() argument
81 smt_init_mib(smc,level) ; in smt_reset_defaults()
83 smc->os.smc_version = SMC_VERSION ; in smt_reset_defaults()
86 smc->sm.last_tok_time[i] = smt_boot_time ; in smt_reset_defaults()
87 smt = &smc->s ; in smt_reset_defaults()
88 smt->attach_s = 0 ; in smt_reset_defaults()
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| /linux-6.12.1/drivers/s390/scsi/ |
| D | zfcp_dbf.c | 1 // SPDX-License-Identifier: GPL-2.0
31 "log level for each debug feature area "
36 return sizeof(struct zfcp_dbf_pay) + offset - ZFCP_DBF_PAY_MAX_REC; in zfcp_dbf_plen()
43 struct zfcp_dbf_pay *pl = &dbf->pay_buf; in zfcp_dbf_pl_write()
46 spin_lock(&dbf->pay_lock); in zfcp_dbf_pl_write()
48 pl->fsf_req_id = req_id; in zfcp_dbf_pl_write()
49 memcpy(pl->area, area, ZFCP_DBF_TAG_LEN); in zfcp_dbf_pl_write()
53 (u16) (length - offset)); in zfcp_dbf_pl_write()
54 memcpy(pl->data, data + offset, rec_length); in zfcp_dbf_pl_write()
55 debug_event(dbf->pay, 1, pl, zfcp_dbf_plen(rec_length)); in zfcp_dbf_pl_write()
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| /linux-6.12.1/drivers/scsi/libsas/ |
| D | sas_expander.c | 1 // SPDX-License-Identifier: GPL-2.0
29 static void sas_port_add_ex_phy(struct sas_port *port, struct ex_phy *ex_phy) in sas_port_add_ex_phy() argument
31 sas_port_add_phy(port, ex_phy->phy); in sas_port_add_ex_phy()
32 ex_phy->port = port; in sas_port_add_ex_phy()
33 ex_phy->phy_state = PHY_DEVICE_DISCOVERED; in sas_port_add_ex_phy()
38 struct expander_device *ex = &dev->ex_dev; in sas_ex_add_parent_port()
39 struct ex_phy *ex_phy = &ex->ex_phy[phy_id]; in sas_ex_add_parent_port()
41 if (!ex->parent_port) { in sas_ex_add_parent_port()
42 ex->parent_port = sas_port_alloc(&dev->rphy->dev, phy_id); in sas_ex_add_parent_port()
44 BUG_ON(!ex->parent_port); in sas_ex_add_parent_port()
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| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | phy-stm32-usbphyc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
13 selects either OTG or HOST controller for the second PHY port. It also sets
19 |_ PHY port#1 _________________ HOST controller
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
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| /linux-6.12.1/drivers/tty/serial/ |
| D | sc16is7xx.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * SC16IS7xx tty serial driver - common code
50 #define SC16IS7XX_TXLVL_REG (0x08) /* TX FIFO level */
51 #define SC16IS7XX_RXLVL_REG (0x09) /* RX FIFO level */
53 * - only on 75x/76x
56 * - only on 75x/76x
59 * - only on 75x/76x
62 * - only on 75x/76x
68 #define SC16IS7XX_TLR_REG (0x07) /* Trigger level */
90 /* IER register bits - write only if (EFR[4] == 1) */
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| /linux-6.12.1/include/linux/usb/ |
| D | tcpm.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright 2015-2017 Google, Inc
59 * struct tcpc_dev - Port configuration and callback functions
60 * @fwnode: Pointer to port fwnode
64 * and cc=Rp-def. This allows the tcpm to provide a fallback
65 * current-limit detection method for the cc=Rp-def case.
82 * Optional; if supported by hardware, called to start dual-role
83 * toggling or single-role connection detection. Toggling stops
94 * Low level drivers can perform chip specific operations, if any.
109 * detect VSAFE0V voltage level at vbus. When detection of VSAFE0V
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| /linux-6.12.1/Documentation/netlabel/ |
| D | draft-ietf-cipso-ipsecurity-01.txt | 12 This Internet Draft provides the high level specification for a Commercial
27 Please check the I-D abstract listing contained in each Internet Draft
46 mandatory access controls and multi-level security. These systems are
88 once in a datagram. All multi-octet fields in the option are defined to be
91 +----------+----------+------//------+-----------//---------+
93 +----------+----------+------//------+-----------//---------+
124 corresponding ASCII representations. Non-related groups of systems may
138 number 1 to represent that same security level. The DOI identifier is used
148 actual security information to be passed. All multi-octet fields in a tag
171 +----------+----------+--------//--------+
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| /linux-6.12.1/Documentation/devicetree/bindings/dma/stm32/ |
| D | st,stm32-dma3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
22 described in "#dma-cells" property description below, using a three-cell
26 - Amelie Delaunay <amelie.delaunay@foss.st.com>
29 - $ref: /schemas/dma/dma-controller.yaml#
33 const: st,stm32mp25-dma3
42 Should contain all of the per-channel DMA interrupts in ascending order
51 power-domains:
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| /linux-6.12.1/Documentation/arch/m68k/ |
| D | buddha-driver.rst | 8 ------------------------------------------------------------------------
11 Buddha-part of the Catweasel Zorro-II version
21 product number: 0 (42 for Catweasel Z-II)
23 Rom-vector: $1000
25 The card should be a Z-II board, size 64K, not for freemem
26 list, Rom-Vektor is valid, no second Autoconfig-board on the
30 as the Amiga Kickstart does: The lower nibble of the 8-Bit
36 otherwise your chance is only 1:16 to find the board :-).
38 The local memory-map is even active when mapped to $e8:
41 $0-$7e Autokonfig-space, see Z-II docs.
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| /linux-6.12.1/Documentation/devicetree/bindings/gpio/ |
| D | nvidia,tegra186-gpio.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
42 implemented by the SoC. Each GPIO is assigned to a port, and a port may
44 alphabetical port name and an integer GPIO name within the port. For
48 of implemented GPIOs within each port varies. GPIO registers within a
49 controller are grouped and laid out according to the port they affect.
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| /linux-6.12.1/Documentation/scsi/ |
| D | advansys.rst | 1 .. SPDX-License-Identifier: GPL-2.0
8 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
9 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
10 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
21 - ABP-480 - Bus-Master CardBus (16 CDB)
24 - ABP510/5150 - Bus-Master ISA (240 CDB)
25 - ABP5140 - Bus-Master ISA PnP (16 CDB)
26 - ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
27 - ABP902/3902 - Bus-Master PCI (16 CDB)
28 - ABP3905 - Bus-Master PCI (16 CDB)
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| /linux-6.12.1/Documentation/admin-guide/ |
| D | thunderbolt.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 some differences at the register level among other things. Connection
18 software connection manager in Linux also advertises security level
21 the software connection manager only supports ``user`` security level and
25 -----------------------------------
27 should be a userspace tool that handles all the low-level details, keeps
31 found in ``Documentation/ABI/testing/sysfs-bus-thunderbolt``.
35 ``/etc/udev/rules.d/99-local.rules``::
44 security levels available. Intel Titan Ridge added one more security level
51 treated as another security level (nopcie).
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| /linux-6.12.1/drivers/parisc/ |
| D | eisa.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * eisa.c - provide support for EISA adapters in PA-RISC machines
10 * Wax ASIC also includes a PS/2 and RS-232 controller, but those are
15 * -----
17 * set an edge trigger level. This may be done on the palo command line
38 #include <asm/parisc-device.h>
67 /* Port ops */
69 static inline unsigned long eisa_permute(unsigned short port) in eisa_permute() argument
71 if (port & 0x300) { in eisa_permute()
72 return 0xfc000000 | ((port & 0xfc00) >> 6) in eisa_permute()
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| /linux-6.12.1/arch/arm64/boot/dts/synaptics/ |
| D | berlin4ct.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
21 compatible = "arm,psci-1.0", "arm,psci-0.2";
26 #address-cells = <1>;
27 #size-cells = <0>;
30 compatible = "arm,cortex-a53";
33 enable-method = "psci";
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| /linux-6.12.1/drivers/xen/events/ |
| D | events_2l.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Xen event channels (2-level ABI)
19 #include <xen/xen-ops.h>
62 static void evtchn_2l_clear_pending(evtchn_port_t port) in evtchn_2l_clear_pending() argument
65 sync_clear_bit(port, BM(&s->evtchn_pending[0])); in evtchn_2l_clear_pending()
68 static void evtchn_2l_set_pending(evtchn_port_t port) in evtchn_2l_set_pending() argument
71 sync_set_bit(port, BM(&s->evtchn_pending[0])); in evtchn_2l_set_pending()
74 static bool evtchn_2l_is_pending(evtchn_port_t port) in evtchn_2l_is_pending() argument
77 return sync_test_bit(port, BM(&s->evtchn_pending[0])); in evtchn_2l_is_pending()
80 static void evtchn_2l_mask(evtchn_port_t port) in evtchn_2l_mask() argument
[all …]
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| /linux-6.12.1/sound/pci/lx6464es/ |
| D | lx_core.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* -*- linux-c -*- *
5 * low-level interface
21 /* low-level register access */
59 unsigned long lx_dsp_reg_read(struct lx6464es *chip, int port);
60 void lx_dsp_reg_write(struct lx6464es *chip, int port, unsigned data);
82 unsigned long lx_plx_reg_read(struct lx6464es *chip, int port);
83 void lx_plx_reg_write(struct lx6464es *chip, int port, u32 data);
96 /* low-level dsp access */
104 /* low-level pipe handling */
[all …]
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| /linux-6.12.1/drivers/gpio/ |
| D | gpio-dwapb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
24 #include "gpiolib-acpi.h"
46 #define DWAPB_DRIVER_NAME "gpio-dwapb"
82 /* Store GPIO context across system-wide suspend/resume transitions */
111 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
143 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2) in gpio_reg_convert()
151 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_read()
152 void __iomem *reg_base = gpio->regs; in dwapb_read()
154 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); in dwapb_read()
160 struct gpio_chip *gc = &gpio->ports[0].gc; in dwapb_write()
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| /linux-6.12.1/Documentation/devicetree/bindings/net/ |
| D | marvell-orion-net.txt | 9 first level describes the ethernet controller itself and the second level
10 describes up to 3 ethernet port nodes within that controller. The reason for
11 the multiple levels is that the port registers are interleaved within a single
12 set of controller registers. Each port node describes port-specific properties.
16 only one port associated. Multiple ports are implemented as multiple single-port
23 - #address-cells: shall be 1.
24 - #size-cells: shall be 0.
25 - compatible: shall be one of "marvell,orion-eth", "marvell,kirkwood-eth".
26 - reg: address and length of the controller registers.
29 - clocks: phandle reference to the controller clock.
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/display/ |
| D | st,stm32mp25-lvds.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
15 LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC)
19 - LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input
21 - LVDS PHY: parallelize the data and drives the LVDS data lanes
22 - LVDS wrapper: handles top-level settings
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| /linux-6.12.1/sound/pcmcia/vx/ |
| D | vxp_ops.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
41 return chip->port + vxp_reg_offset[reg]; in vxp_reg_addr()
45 * snd_vx_inb - read a byte from the register
54 * snd_vx_outb - write a byte on the register
73 * vx_check_magic - check the magic word on xilinx
87 dev_err(chip->card->dev, "cannot find xilinx magic word (%x)\n", c); in vx_check_magic()
88 return -EIO; in vx_check_magic()
93 * vx_reset_dsp - reset the DSP
103 vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_DSP_RESET_MASK); in vxp_reset_dsp()
107 chip->regCDSP &= ~VXP_CDSP_DSP_RESET_MASK; in vxp_reset_dsp()
[all …]
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| /linux-6.12.1/drivers/pinctrl/ |
| D | pinctrl-cy8c95x0.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * CY8C95X0 20/40/60 pin I2C GPIO port expander with interrupt support
28 #include <linux/pinctrl/pinconf-generic.h>
41 /* Port Select configures the port */
43 /* Port settings, write PORTSEL first */
69 (CY8C95X0_VIRTUAL + (x) - CY8C95X0_PORTSEL + (p) * MUXED_STRIDE)
92 { "irq-gpios", &cy8c95x0_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER },
117 * Since first controller (gpio-sch.c) and second
118 * (gpio-dwapb.c) are at the fixed bases, we may safely
130 * struct cy8c95x0_pinctrl - driver data
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|