bindings/gpio/nvidia%2Ctegra186-gpio.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Thierry Reding <thierry.reding@gmail.com>
11   - Jon Hunter <jonathanh@nvidia.com>
42     implemented by the SoC. Each GPIO is assigned to a port, and a port may
44     alphabetical port name and an integer GPIO name within the port. For
48     of implemented GPIOs within each port varies. GPIO registers within a
49     controller are grouped and laid out according to the port they affect.
51     The mapping from port name to the GPIO controller that implements that
52     port, and the mapping from port name to register offset within a
53     controller, are both extremely non-linear. The header file
54     <dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In
65     module and the sets-of-ports as "controllers".
69     one of the interrupt signals generated by a set-of-ports. The intent is
71     different CPUs to each handle subsets of the interrupts within a port.
72     The status of each of these per-port-set signals is reported via a
76     GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could
82       - nvidia,tegra186-gpio
83       - nvidia,tegra186-gpio-aon
84       - nvidia,tegra194-gpio
85       - nvidia,tegra194-gpio-aon
86       - nvidia,tegra234-gpio
87       - nvidia,tegra234-gpio-aon
89   reg-names:
91       - const: security
92       - const: gpio
97       - description: Security configuration registers.
98       - description: |
112   gpio-controller: true
114   "#gpio-cells":
119         - The first cell is the pin number.
120           See <dt-bindings/gpio/tegra186-gpio.h>.
121         - The second cell contains flags:
122           - Bit 0 specifies polarity
123             - 0: Active-high (normal).
124             - 1: Active-low (inverted).
127   interrupt-controller: true
129   "#interrupt-cells":
134         - The first cell is the GPIO number.
135           See <dt-bindings/gpio/tegra186-gpio.h>.
136         - The second cell is contains flags:
137           - Bits [3:0] indicate trigger type and level:
138             - 1: Low-to-high edge triggered.
139             - 2: High-to-low edge triggered.
140             - 4: Active high level-sensitive.
141             - 8: Active low level-sensitive.
147   - if:
152               - nvidia,tegra186-gpio
153               - nvidia,tegra194-gpio
154               - nvidia,tegra234-gpio
161   - if:
166               - nvidia,tegra186-gpio-aon
167               - nvidia,tegra194-gpio-aon
168               - nvidia,tegra234-gpio-aon
176   - compatible
177   - reg
178   - reg-names
179   - interrupts
184   - |
185     #include <dt-bindings/interrupt-controller/irq.h>
188         compatible = "nvidia,tegra186-gpio";
189         reg-names = "security", "gpio";
198         gpio-controller;
199         #gpio-cells = <2>;
200         interrupt-controller;
201         #interrupt-cells = <2>;
205         compatible = "nvidia,tegra186-gpio-aon";
206         reg-names = "security", "gpio";
210         gpio-controller;
211         #gpio-cells = <2>;
212         interrupt-controller;
213         #interrupt-cells = <2>;