| /linux-6.12.1/arch/arm/boot/dts/rockchip/ |
| D | rv1126.dtsi | 233 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
247 clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
261 clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
276 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
287 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
298 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
309 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
320 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
331 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
342 clocks = <&pmucru CLK_PWM1>, <&pmucru PCLK_PWM1>;
[all …]
|
| /linux-6.12.1/Documentation/devicetree/bindings/clock/ |
| D | rockchip,px30-cru.yaml | 34 - rockchip,px30-pmucru
48 - description: Clock for both PMUCRU and CRU
49 - description: Clock for CRU (sourced from PMUCRU)
101 pmucru: clock-controller@ff2bc000 {
102 compatible = "rockchip,px30-pmucru";
114 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
|
| D | rockchip,rk3568-cru.yaml | 26 - rockchip,rk3568-pmucru
61 pmucru: clock-controller@fdd00000 {
62 compatible = "rockchip,rk3568-pmucru";
|
| D | rockchip,rk3399-cru.yaml | 36 - rockchip,rk3399-pmucru
71 pmucru: clock-controller@ff750000 {
72 compatible = "rockchip,rk3399-pmucru";
|
| D | rockchip,rv1126-cru.yaml | 22 - rockchip,rv1126-pmucru
|
| /linux-6.12.1/arch/arm64/boot/dts/rockchip/ |
| D | rk356x.dtsi | 452 pmucru: clock-controller@fdd00000 { label
453 compatible = "rockchip,rk3568-pmucru";
466 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
468 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
476 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
489 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
502 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
513 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
524 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
535 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
[all …]
|
| D | rk3566-powkiddy-rgb30.dts | 16 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
17 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
|
| D | rk3566-powkiddy-rk2023.dts | 16 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
17 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
|
| D | rk3566-powkiddy-rgb10max3.dts | 20 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
21 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
|
| D | rk3568.dtsi | 54 clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>,
258 clocks = <&pmucru CLK_PCIEPHY0_REF>,
262 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
|
| D | rk3399-base.dtsi | 1318 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1331 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1344 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1346 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1359 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1361 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1374 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1376 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1392 clocks = <&pmucru PCLK_RKPWM_PMU>;
1402 clocks = <&pmucru PCLK_RKPWM_PMU>;
[all …]
|
| D | rk3566-anbernic-rg353x.dtsi | 81 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
82 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
|
| D | rk3566-anbernic-rg-arc.dtsi | 79 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
80 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
|
| D | rk3566-box-demo.dts | 73 clocks = <&pmucru CLK_RTC_32K>;
451 clocks = <&pmucru CLK_RTC_32K>;
469 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
| D | rk3566-anbernic-rg503.dts | 170 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
171 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
|
| D | rk3566-pinetab2.dtsi | 264 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
265 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
267 assigned-clock-parents = <&pmucru CLK_RTC32K_FRAC>;
923 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
| D | px30.dtsi | 377 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
832 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
849 pmucru: clock-controller@ff2bc000 { label
850 compatible = "rockchip,px30-pmucru";
859 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
860 <&pmucru SCLK_WIFI_PMU>;
876 clocks = <&pmucru SCLK_USBPHY_REF>;
906 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
1397 clocks = <&pmucru PCLK_GPIO0_PMU>;
|
| D | rk3566-powkiddy-x55.dts | 351 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
352 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
907 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
| D | rk3566-radxa-cm3-io.dts | 268 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
| D | rk3568-fastrhino-r66s.dtsi | 454 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
|
| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | rockchip,pcie3-phy.yaml | 106 clocks = <&pmucru CLK_PCIE30PHY_REF_M>,
107 <&pmucru CLK_PCIE30PHY_REF_N>,
|
| D | phy-rockchip-naneng-combphy.yaml | 132 clocks = <&pmucru CLK_PCIEPHY0_REF>,
136 assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
|
| D | rockchip,px30-dsi-dphy.yaml | 65 clocks = <&pmucru 13>, <&cru 12>;
|
| /linux-6.12.1/include/dt-bindings/clock/ |
| D | rk3568-cru.h | 10 /* pmucru-clocks indices */
12 /* pmucru plls */
16 /* pmucru clocks */
|
| D | rockchip,rv1126-cru.h | 10 /* pmucru-clocks indices */
|