| /linux-6.12.1/Documentation/devicetree/bindings/pci/ |
| D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
8 - reg: physical base address (0x79000000) and length (0x900000) for controller
11 - reg-names: not required
12 - interrupts: A list of 16 interrupt outputs of the controller, starting from
14 - interrupt-names: not required
16 Each PCIe node needs to have property msi-parent that points to an MSI
25 compatible = "apm,xgene1-msi";
[all …]
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| D | pci-armada8k.txt | 1 * Marvell Armada 7K/8K PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "marvell,armada8k-pcie"
8 - reg: must contain two register regions
9 - the control register region
10 - the config space region
11 - reg-names:
12 - "ctrl" for the control register region
13 - "config" for the config space region
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/skylakex/ |
| D | uncore-io.json | 13 …PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could…
15 "UMask": "0x4",
29 …PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could…
44 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
48 "FCMask": "0x4",
55 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
59 "FCMask": "0x4",
66 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
70 "FCMask": "0x4",
77 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/cascadelakex/ |
| D | uncore-io.json | 13 …PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could…
15 "UMask": "0x4",
29 …PCIe card of any size (x16,x8,x4) that is plugged directly into one of the PCIe slots. Part0 could…
44 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-3",
48 "FCMask": "0x4",
55 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
59 "FCMask": "0x4",
66 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
70 "FCMask": "0x4",
77 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/st/ |
| D | spear1310.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
15 compatible = "st,spear-spics-gpio";
17 st-spics,peripcfg-reg = <0x3b0>;
18 st-spics,sw-enable-bit = <12>;
19 st-spics,cs-value-bit = <11>;
20 st-spics,cs-enable-mask = <3>;
21 st-spics,cs-enable-shift = <8>;
22 gpio-controller;
23 #gpio-cells = <2>;
27 compatible = "st,spear1310-miphy";
[all …]
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| D | spear1340.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
16 compatible = "st,spear-spics-gpio";
18 st-spics,peripcfg-reg = <0x42c>;
19 st-spics,sw-enable-bit = <21>;
20 st-spics,cs-value-bit = <20>;
21 st-spics,cs-enable-mask = <3>;
22 st-spics,cs-enable-shift = <18>;
23 gpio-controller;
24 #gpio-cells = <2>;
29 compatible = "st,spear1340-miphy";
[all …]
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| /linux-6.12.1/drivers/phy/broadcom/ |
| D | phy-bcm-sr-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
29 #define MHB_PWR_ARR_POWEROK 0x4
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
56 * @base: base register of PCIe SS
60 * @phys: array of PCIe PHYs
72 * PCIe PIPEMUX lookup table
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/emeraldrapids/ |
| D | uncore-io.json | 182 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
190 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
191 "UMask": "0x4",
195 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
203 …": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane…
208 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
216 …": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane…
221 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
229 …": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane…
234 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
[all …]
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| /linux-6.12.1/tools/perf/pmu-events/arch/x86/sapphirerapids/ |
| D | uncore-io.json | 182 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0-7",
190 "PublicDescription": "PCIe Completion Buffer Inserts of completions with data : Part 0-7",
191 "UMask": "0x4",
195 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 0",
203 …": "PCIe Completion Buffer Inserts of completions with data : Part 0 : x16 card plugged in to Lane…
208 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 1",
216 …": "PCIe Completion Buffer Inserts of completions with data : Part 1 : x16 card plugged in to Lane…
221 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 2",
229 …": "PCIe Completion Buffer Inserts of completions with data : Part 2 : x16 card plugged in to Lane…
234 "BriefDescription": "PCIe Completion Buffer Inserts of completions with data: Part 3",
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/marvell/ |
| D | armada-385.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 #address-cells = <1>;
20 #size-cells = <0>;
21 enable-method = "marvell,armada-380-smp";
25 compatible = "arm,cortex-a9";
30 compatible = "arm,cortex-a9";
36 pciec: pcie {
[all …]
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| D | armada-39x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
37 compatible = "arm,cortex-a9";
[all …]
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| D | armada-xp-mv78230.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
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| D | armada-xp-mv78260.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
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| D | armada-xp-mv78460.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
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| /linux-6.12.1/Documentation/devicetree/bindings/phy/ |
| D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
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| D | airoha,en7581-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/airoha,en7581-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Airoha EN7581 PCI-Express PHY
10 - Lorenzo Bianconi <lorenzo@kernel.org>
13 The PCIe PHY supports physical layer functionality for PCIe Gen2/Gen3 port.
17 const: airoha,en7581-pcie-phy
21 - description: PCIE analog base address
22 - description: PCIE lane0 base address
[all …]
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| /linux-6.12.1/drivers/pci/controller/ |
| D | pcie-rcar.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * PCIe driver for Renesas R-Car SoCs
4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd
40 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
49 /* PCIe address reg & mask */
58 #define PCICONF(x) (0x010000 + ((x) * 0x4))
60 #define PMCAP(x) (0x010040 + ((x) * 0x4))
61 #define MSICAP(x) (0x010050 + ((x) * 0x4))
66 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
67 #define VCCAP(x) (0x010100 + ((x) * 0x4))
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/ti/omap/ |
| D | dra74x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
16 compatible = "arm,cortex-a15";
18 operating-points-v2 = <&cpu0_opp_table>;
21 clock-names = "cpu";
23 clock-latency = <300000>; /* From omap-cpufreq driver */
26 #cooling-cells = <2>; /* min followed by max */
28 vbb-supply = <&abb_mpu>;
40 compatible = "arm,cortex-a15-pmu";
41 interrupt-parent = <&wakeupgen>;
[all …]
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| D | dra72x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
20 compatible = "arm,cortex-a15-pmu";
21 interrupt-parent = <&wakeupgen>;
27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
28 compatible = "ti,sysc-omap4", "ti,sysc";
29 reg = <0x5b000 0x4>,
30 <0x5b010 0x4>;
31 reg-names = "rev", "sysc";
32 ti,sysc-midle = <SYSC_IDLE_FORCE>,
[all …]
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| /linux-6.12.1/arch/arm/boot/dts/airoha/ |
| D | en7523.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 #include <dt-bindings/interrupt-controller/irq.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/clock/en7523-clk.h>
9 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <1>;
13 reserved-memory {
14 #address-cells = <1>;
[all …]
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| /linux-6.12.1/arch/powerpc/boot/dts/fsl/ |
| D | mpc8544ds.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8544si-pre.dtsi"
16 reg = <0 0 0 0>; // Filled by U-Boot
33 clock-frequency = <66666666>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
35 interrupt-map = <
40 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
41 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
46 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
48 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0>;
[all …]
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| D | ge_imp3a.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
11 /include/ "p2020si-pre.dtsi"
28 0x4 0x0 0x0 0xfc000000 0x00008000
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
39 bank-width = <2>;
40 device-width = <1>;
45 read-only;
[all …]
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| /linux-6.12.1/arch/arm64/boot/dts/apm/ |
| D | apm-storm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
[all …]
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| /linux-6.12.1/drivers/pinctrl/mvebu/ |
| D | pinctrl-armada-370.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 #include "pinctrl-mvebu.h"
37 MPP_FUNCTION(0x1, "vdd", "cpu-pd")),
42 MPP_FUNCTION(0x4, "spi1", "sck"),
48 MPP_FUNCTION(0x4, "tdm", "rst"),
53 MPP_FUNCTION(0x4, "tdm", "dtx"),
59 MPP_FUNCTION(0x4, "tdm", "drx"),
71 MPP_FUNCTION(0x4, "tdm", "fsync"),
78 MPP_FUNCTION(0x4, "spi0", "cs1"),
[all …]
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| /linux-6.12.1/arch/powerpc/boot/dts/ |
| D | redwood.dts | 11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
26 #address-cells = <1>;
27 #size-cells = <0>;
33 clock-frequency = <0>; /* Filled in by U-Boot */
34 timebase-frequency = <0>; /* Filled in by U-Boot */
35 i-cache-line-size = <32>;
36 d-cache-line-size = <32>;
[all …]
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