dts/marvell/armada-385.dtsi

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 #include "armada-38x.dtsi"
19 		#address-cells = <1>;
20 		#size-cells = <0>;
21 		enable-method = "marvell,armada-380-smp";
25 			compatible = "arm,cortex-a9";
30 			compatible = "arm,cortex-a9";
36 		pciec: pcie {
37 			compatible = "marvell,armada-370-pcie";
41 			#address-cells = <3>;
42 			#size-cells = <2>;
44 			msi-parent = <&mpic>;
45 			bus-range = <0x00 0xff>;
58 				0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
59 				0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
62 			 * This port can be either x4 or x1. When
63 			 * configured in x4 by the bootloader, then
64 			 * pcie@4,0 is not available.
66 			pcie1: pcie@1,0 {
68 				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
70 				#address-cells = <3>;
71 				#size-cells = <2>;
72 				interrupt-names = "intx";
73 				interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
74 				#interrupt-cells = <1>;
77 				bus-range = <0x00 0xff>;
78 				interrupt-map-mask = <0 0 0 7>;
79 				interrupt-map = <0 0 0 1 &pcie1_intc 0>,
83 				marvell,pcie-port = <0>;
84 				marvell,pcie-lane = <0>;
87 				pcie1_intc: interrupt-controller {
88 					interrupt-controller;
89 					#interrupt-cells = <1>;
94 			pcie2: pcie@2,0 {
96 				assigned-addresses = <0x82001000 0 0x40000 0 0x2000>;
98 				#address-cells = <3>;
99 				#size-cells = <2>;
100 				interrupt-names = "intx";
101 				interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
102 				#interrupt-cells = <1>;
105 				bus-range = <0x00 0xff>;
106 				interrupt-map-mask = <0 0 0 7>;
107 				interrupt-map = <0 0 0 1 &pcie2_intc 0>,
111 				marvell,pcie-port = <1>;
112 				marvell,pcie-lane = <0>;
115 				pcie2_intc: interrupt-controller {
116 					interrupt-controller;
117 					#interrupt-cells = <1>;
122 			pcie3: pcie@3,0 {
124 				assigned-addresses = <0x82001800 0 0x44000 0 0x2000>;
126 				#address-cells = <3>;
127 				#size-cells = <2>;
128 				interrupt-names = "intx";
129 				interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
130 				#interrupt-cells = <1>;
133 				bus-range = <0x00 0xff>;
134 				interrupt-map-mask = <0 0 0 7>;
135 				interrupt-map = <0 0 0 1 &pcie3_intc 0>,
139 				marvell,pcie-port = <2>;
140 				marvell,pcie-lane = <0>;
143 				pcie3_intc: interrupt-controller {
144 					interrupt-controller;
145 					#interrupt-cells = <1>;
150 			 * x1 port only available when pcie@1,0 is
153 			pcie4: pcie@4,0 {
155 				assigned-addresses = <0x82002000 0 0x48000 0 0x2000>;
157 				#address-cells = <3>;
158 				#size-cells = <2>;
159 				interrupt-names = "intx";
160 				interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
161 				#interrupt-cells = <1>;
162 				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
163 					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
164 				bus-range = <0x00 0xff>;
165 				interrupt-map-mask = <0 0 0 7>;
166 				interrupt-map = <0 0 0 1 &pcie4_intc 0>,
170 				marvell,pcie-port = <3>;
171 				marvell,pcie-lane = <0>;
174 				pcie4_intc: interrupt-controller {
175 					interrupt-controller;
176 					#interrupt-cells = <1>;
184 	compatible = "marvell,mv88f6820-pinctrl";