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/linux-6.12.1/Documentation/devicetree/bindings/gpio/
Dnuvoton,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim LIU <JJLIU0@nuvoton.com>
20 to 64 output pins, and up to 64 input pins, the pin is only for GPI or GPO.
22 - Support interrupt option for each input port and various interrupt
23 sensitivity options (level-high, level-low, edge-high, edge-low)
24 - ngpios is number of nuvoton,input-ngpios GPIO lines and nuvoton,output-ngpios GPIO lines.
25 nuvoton,input-ngpios GPIO lines is only for GPI.
26 nuvoton,output-ngpios GPIO lines is only for GPO.
[all …]
Daspeed,sgpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
17 - Support interrupt option for each input port and various interrupt
18 sensitivity option (level-high, level-low, edge-high, edge-low)
19 - Support reset tolerance option for each output port
20 - Directly connected to APB bus and its shift clock is from APB bus clock
22 - Co-work with external signal-chained TTL components (74LV165/74LV595)
27 - aspeed,ast2400-sgpio
[all …]
Dgpio.txt5 -----------------
7 GPIO properties should be named "[<name>-]gpios", with <name> being the purpose
8 of this GPIO for the device. While a non-existent <name> is considered valid
10 for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old
24 and bit-banged data signals:
27 gpio-controller;
28 #gpio-cells = <2>;
32 data-gpios = <&gpio1 12 0>,
44 recommended to use the two-cell approach.
48 include/dt-bindings/gpio/gpio.h whenever possible:
[all …]
/linux-6.12.1/drivers/gpio/
Dgpio-em.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Emma Mobile GPIO Support - GIO
61 return ioread32(p->base0 + offs); in em_gio_read()
63 return ioread32(p->base1 + (offs - GIO_IDT0)); in em_gio_read()
70 iowrite32(value, p->base0 + offs); in em_gio_write()
72 iowrite32(value, p->base1 + (offs - GIO_IDT0)); in em_gio_write()
94 ret = gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d)); in em_gio_irq_reqres()
96 dev_err(p->gpio_chip.parent, in em_gio_irq_reqres()
108 gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d)); in em_gio_irq_relres()
131 return -EINVAL; in em_gio_irq_set_type()
[all …]
Dgpio-aspeed-sgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
52 * The "rdata" register returns the output value when the GPIO is
53 * configured as an output.
110 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in bank_reg()
112 return gpio->base + bank->rdata_reg; in bank_reg()
114 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in bank_reg()
116 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in bank_reg()
118 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in bank_reg()
120 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in bank_reg()
122 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in bank_reg()
[all …]
Dgpio-realtek-otto.c1 // SPDX-License-Identifier: GPL-2.0-only
24 /* Clear bit (0) for input, set bit (1) for output */
42 * realtek_gpio_ctrl - Realtek Otto GPIO driver data
49 * @bank_read: Read a bank setting as a single 32-bit value
50 * @bank_write: Write a bank setting as a single 32-bit value
53 * The DIR, DATA, and ISR registers consist of four 8-bit port values, packed
54 * into a single 32-bit register. Use @bank_read (@bank_write) to get (assign)
55 * a value from (to) these registers. The IMR register consists of four 16-bit
56 * port values, packed into two 32-bit registers. Use @imr_line_pos to get the
57 * bit shift of the 2-bit field for a line's IMR settings. Shifts larger than
[all …]
Dgpio-aggregator.c1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2019-2020 Glider bv
7 #define DRV_NAME "gpio-aggregator"
50 lookups = krealloc(aggr->lookups, struct_size(lookups, table, *n + 2), in aggr_add_gpio()
53 return -ENOMEM; in aggr_add_gpio()
55 lookups->table[*n] = GPIO_LOOKUP_IDX(key, hwnum, NULL, *n, 0); in aggr_add_gpio()
58 memset(&lookups->table[*n], 0, sizeof(lookups->table[*n])); in aggr_add_gpio()
60 aggr->lookups = lookups; in aggr_add_gpio()
66 char *args = skip_spaces(aggr->args); in aggr_parse()
74 return -ENOMEM; in aggr_parse()
[all …]
Dgpio-npcm-sgpio.c1 // SPDX-License-Identifier: GPL-2.0
143 return gpio->base + bank->rdata_reg; in bank_reg()
145 return gpio->base + bank->wdata_reg; in bank_reg()
147 return gpio->base + bank->event_config; in bank_reg()
149 return gpio->base + bank->event_status; in bank_reg()
152 dev_WARN(gpio->chip.parent, "Getting here is an error condition"); in bank_reg()
175 *offset -= internal->nout_sgpio; in npcm_sgpio_irqd_to_data()
184 in_port = GPIO_BANK(gpio->nin_sgpio); in npcm_sgpio_init_port()
185 if (GPIO_BIT(gpio->nin_sgpio) > 0) in npcm_sgpio_init_port()
188 out_port = GPIO_BANK(gpio->nout_sgpio); in npcm_sgpio_init_port()
[all …]
Dgpio-cadence.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2017-2018 Cadence
8 * Boris Brezillon <boris.brezillon@free-electrons.com>
43 raw_spin_lock_irqsave(&chip->bgpio_lock, flags); in cdns_gpio_request()
45 iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) & ~BIT(offset), in cdns_gpio_request()
46 cgpio->regs + CDNS_GPIO_BYPASS_MODE); in cdns_gpio_request()
48 raw_spin_unlock_irqrestore(&chip->bgpio_lock, flags); in cdns_gpio_request()
57 raw_spin_lock_irqsave(&chip->bgpio_lock, flags); in cdns_gpio_free()
59 iowrite32(ioread32(cgpio->regs + CDNS_GPIO_BYPASS_MODE) | in cdns_gpio_free()
60 (BIT(offset) & cgpio->bypass_orig), in cdns_gpio_free()
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
[all …]
Dintel,pinctrl-keembay.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
14 of pin directions, input/output values and configuration
19 const: intel,keembay-pinctrl
24 gpio-controller: true
26 '#gpio-cells':
29 ngpios:
[all …]
Dbrcm,nsp-gpio.txt4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
26 - interrupt-controller:
29 - gpio-ranges:
30 Specifies the mapping between gpio controller and pin-controllers pins.
[all …]
Dst,stm32-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre TORGUE <alexandre.torgue@foss.st.com>
15 controller. It controls the input/output settings on the available pins and
16 also provides ability to multiplex and configure the output of various
17 on-chip controllers onto these pads.
22 - st,stm32f429-pinctrl
23 - st,stm32f469-pinctrl
[all …]
/linux-6.12.1/Documentation/admin-guide/gpio/
Dgpio-sim.rst1 .. SPDX-License-Identifier: GPL-2.0-or-later
6 The configfs GPIO Simulator (gpio-sim) provides a way to create simulated GPIO
12 ------------------------
14 The gpio-sim module registers a configfs subsystem called ``'gpio-sim'``. For
21 **Group:** ``/config/gpio-sim``
23 This is the top directory of the gpio-sim configfs tree.
25 **Group:** ``/config/gpio-sim/gpio-device``
27 **Attribute:** ``/config/gpio-sim/gpio-device/dev_name``
29 **Attribute:** ``/config/gpio-sim/gpio-device/live``
32 attribute is read-only and allows the user-space to read the platform device
[all …]
/linux-6.12.1/arch/arm64/boot/dts/microchip/
Dsparx5_pcb134_board.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
10 gpio-restart {
11 compatible = "gpio-restart";
16 i2c0_imux: i2c-mux-0 {
17 compatible = "i2c-mux-pinctrl";
18 #address-cells = <1>;
19 #size-cells = <0>;
20 i2c-parent = <&i2c0>;
23 i2c0_emux: i2c-mux-1 {
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/leds/
Dleds-lgm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/leds/leds-lgm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel Lightning Mountain (LGM) SoC LED Serial Shift Output (SSO) Controller driver
10 - Zhu, Yi Xin <Yixin.zhu@intel.com>
11 - Amireddy Mallikarjuna reddy <mallikarjunax.reddy@intel.com>
15 const: intel,lgm-ssoled
23 clock-names:
25 - const: sso
[all …]
/linux-6.12.1/arch/riscv/boot/dts/sophgo/
Dcv18xx.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/sophgo,cv1800.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <25000000>;
24 d-cache-block-size = <64>;
[all …]
Dsg2042.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/clock/sophgo,sg2042-clkgen.h>
8 #include <dt-bindings/clock/sophgo,sg2042-pll.h>
9 #include <dt-bindings/clock/sophgo,sg2042-rpgate.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/reset/sophgo,sg2042-reset.h>
13 #include "sg2042-cpus.dtsi"
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
/linux-6.12.1/arch/riscv/boot/dts/thead/
Dth1520.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/clock/thead,th1520-clk-ap.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <3000000>;
24 riscv,isa-base = "rv64i";
25 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
[all …]
/linux-6.12.1/arch/arm/boot/dts/microchip/
Dlan966x-pcb8309.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x_pcb8309.dts - Device Tree file for PCB8309
5 /dts-v1/;
7 #include "dt-bindings/phy/phy-lan966x-serdes.h"
10 model = "Microchip EVB - LAN9662";
11 compatible = "microchip,lan9662-pcb8309", "microchip,lan9662", "microchip,lan966";
20 stdout-path = "serial0:115200n8";
23 gpio-restart {
24 compatible = "gpio-restart";
29 i2c-mux {
[all …]
/linux-6.12.1/include/linux/gpio/
Ddriver.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/pinctrl/pinconf-generic.h>
48 * struct gpio_irq_chip - GPIO interrupt controller
78 * If non-NULL, will be set as the parent of this GPIO interrupt
90 * hardware IRQs correspond to the GPIO index 0..ngpio-1 (see the
98 * HWIRQ, return -EINVAL, but also make sure to fill in @valid_mask and
113 * &gpiochip_populate_parent_fwspec_twocell will be used. A four-cell
269 * is passed a bitmap in "valid_mask" and it will have ngpios
270 * bits from 0..(ngpios-1) set to "1" as in valid. The callback can
276 unsigned int ngpios);
[all …]
/linux-6.12.1/drivers/pinctrl/qcom/
Dpinctrl-msm.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <linux/pinctrl/pinconf-generic.h>
32 #include "../pinctrl-utils.h"
34 #include "pinctrl-msm.h"
41 * struct msm_pinctrl - state for a pinctrl-msm device
89 return readl(pctrl->regs[g->tile] + g->name##_reg); \
94 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
106 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0; in MSM_ACCESSOR()
115 return pctrl->soc->ngroups; in msm_get_groups_count()
123 return pctrl->soc->groups[group].grp.name; in msm_get_group_name()
[all …]
Dpinctrl-msm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
38 * struct msm_pingroup - Qualcomm pingroup definition
46 * @io_reg: Offset of the register holding input/output bits for this group.
55 * @oe_bit: Offset in @ctl_reg for controlling output enable.
57 * @out_bit: Offset in @io_reg for the output bit value.
118 * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
120 * @wakeirq: The interrupt at the always-on interrupt controller
128 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
143 * @egpio_func: If non-zero then this SoC supports eGPIO. Even though in
144 * hardware this is a mux 1-level above the TLMM, we'll treat
[all …]
/linux-6.12.1/drivers/pinctrl/actions/
Dpinctrl-owl.h1 // SPDX-License-Identifier: GPL-2.0+
6 * Author: David Liu <liuwei@actions-semi.com>
28 .drv_reg = -1, \
29 .drv_shift = -1, \
30 .drv_width = -1, \
31 .sr_reg = -1, \
32 .sr_shift = -1, \
33 .sr_width = -1, \
41 .mfpctl_reg = -1, \
42 .mfpctl_shift = -1, \
[all …]
/linux-6.12.1/arch/riscv/boot/dts/microchip/
Dmpfs-m100pfsevp.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Original all-in-one devicetree:
4 * Copyright (C) 2021-2022 - Wolfgang Grandegger <wg@aries-embedded.de>
6 * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com>
8 /dts-v1/;
11 #include "mpfs-m100pfs-fabric.dtsi"
30 stdout-path = "serial1:115200n8";
60 ngpios = <14>;
63 pmic-irq-hog {
64 gpio-hog;
[all …]

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