/linux-6.12.1/Documentation/devicetree/bindings/pci/ |
D | samsung,exynos-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Marek Szyprowski <m.szyprowski@samsung.com> 11 - Jaehoon Chung <jh80.chung@samsung.com> 16 snps,dw-pcie.yaml. 19 - $ref: /schemas/pci/snps,dw-pcie.yaml# 23 const: samsung,exynos5433-pcie 27 - description: Data Bus Interface (DBI) registers. [all …]
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D | ti,am65-pci-host.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/ 4 --- 5 $id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Kishon Vijay Abraham I <kishon@ti.com> 14 - $ref: /schemas/pci/pci-host-bridge.yaml# 19 - ti,am654-pcie-rc 20 - ti,keystone-pcie 25 reg-names: [all …]
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D | socionext,uniphier-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 13 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml. 16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 19 - $ref: /schemas/pci/snps,dw-pcie.yaml# 24 - socionext,uniphier-pcie 30 reg-names: 33 - const: dbi [all …]
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D | snps,dw-pcie-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-common.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Jingoo Han <jingoohan1@gmail.com> 11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com> 23 Interface - DBI. In accordance with the reference manual the register 24 configuration space belongs to the Configuration-Dependent Module (CDM) 25 and is split up into several sub-parts Standard PCIe configuration 26 space, Port Logic Registers (PL), Shadow Config-space Registers, [all …]
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D | toshiba,visconti-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/toshiba,visconti-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 16 - $ref: /schemas/pci/snps,dw-pcie.yaml# 20 const: toshiba,visconti-pcie 24 - description: Data Bus Interface (DBI) registers. 25 - description: PCIe configuration space region. 26 - description: Visconti specific additional registers. [all …]
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D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Jingoo Han <jingoohan1@gmail.com> 11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com> 16 # Please create a separate DT-schema for your DWC PCIe Root Port controller 17 # and make sure it's assigned with the vendor-specific compatible string. 21 const: snps,dw-pcie 23 - compatible [all …]
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D | fsl,layerscape-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Frank Li <Frank.Li@nxp.com> 16 which is used to describe the PLL settings at the time of chip-reset. 26 - enum: 27 - fsl,ls1012a-pcie 28 - fsl,ls1021a-pcie 29 - fsl,ls1028a-pcie [all …]
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D | nvidia,tegra194-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 - Vidya Sagar <vidyas@nvidia.com> 16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of 20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device 26 - nvidia,tegra194-pcie [all …]
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/linux-6.12.1/arch/arm64/boot/dts/marvell/ |
D | cn9132-db.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * Device tree for the CN9132-DB board. 8 #include "cn9131-db.dtsi" 12 "marvell,armada-ap807-quad", "marvell,armada-ap807"; 20 cp2_reg_usb3_vbus0: regulator-7 { 21 compatible = "regulator-fixed"; 22 regulator-name = "cp2-xhci0-vbus"; 23 regulator-min-microvolt = <5000000>; 24 regulator-max-microvolt = <5000000>; 25 enable-active-high; [all …]
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D | cn9130-crb-A.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 6 #include "cn9130-crb.dtsi" 9 model = "Marvell Armada CN9130-CRB-A"; 14 num-lanes = <4>; 15 num-viewport = <8>; 21 iommu-map = 25 iommu-map-mask = <0x031f>; 30 usb-phy = <&cp0_usb3_0_phy0>; 31 phy-names = "usb"; 36 usb-phy = <&cp0_usb3_0_phy1>; [all …]
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D | cn9130-crb-B.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 6 #include "cn9130-crb.dtsi" 9 model = "Marvell Armada CN9130-CRB-B"; 14 num-lanes = <1>; 15 num-viewport = <8>; 18 iommu-map = 22 iommu-map-mask = <0x031f>; 27 sata-port@0 { 36 usb-phy = <&cp0_usb3_0_phy0>; 37 phy-names = "usb"; [all …]
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D | cn9131-db.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * Device tree for the CN9131-DB board. 8 #include "cn9130-db.dtsi" 12 "marvell,armada-ap807-quad", "marvell,armada-ap807"; 21 cp1_reg_usb3_vbus0: regulator-6 { 22 compatible = "regulator-fixed"; 23 pinctrl-names = "default"; 24 pinctrl-0 = <&cp1_xhci0_vbus_pins>; 25 regulator-name = "cp1-xhci0-vbus"; 26 regulator-min-microvolt = <5000000>; [all …]
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D | armada-8040-mcbin.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 #include "armada-8040.dtsi" 10 #include <dt-bindings/gpio/gpio.h> 14 compatible = "marvell,armada8040-mcbin", "marvell,armada8040", 15 "marvell,armada-ap806-quad", "marvell,armada-ap806"; 18 stdout-path = "serial0:115200n8"; 34 v_3_3: regulator-3-3v { 35 compatible = "regulator-fixed"; 36 regulator-name = "v_3_3"; 37 regulator-min-microvolt = <3300000>; [all …]
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D | cn9130-db.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * Device tree for the CN9130-DB board. 10 #include <dt-bindings/gpio/gpio.h> 14 stdout-path = "serial0:115200n8"; 33 ap0_reg_sd_vccq: regulator-1 { 34 compatible = "regulator-gpio"; 35 regulator-name = "ap0_sd_vccq"; 36 regulator-min-microvolt = <1800000>; 37 regulator-max-microvolt = <3300000>; 42 cp0_reg_usb3_vbus0: regulator-2 { [all …]
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D | armada-8040-puzzle-m801.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 * Device Tree file for IEI Puzzle-M801 9 #include "armada-8040.dtsi" 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/leds/common.h> 15 model = "IEI-Puzzle-M801"; 16 compatible = "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"; 28 stdout-path = "serial0:115200n8"; 37 v_3_3: regulator-3-3v { 38 compatible = "regulator-fixed"; [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
D | dml2_core_utils.c | 1 // SPDX-License-Identifier: MIT 9 *remainder = ((dividend / divisor) - (int)(dividend / divisor) > 0); in dml2_core_utils_div_rem() 77 if (!fail_only || support->ScaleRatioAndTapsSupport == 0) in dml2_core_utils_print_mode_support_info() 78 dml2_printf("DML: support: ScaleRatioAndTapsSupport = %d\n", support->ScaleRatioAndTapsSupport); in dml2_core_utils_print_mode_support_info() 79 if (!fail_only || support->SourceFormatPixelAndScanSupport == 0) in dml2_core_utils_print_mode_support_info() 80 …dml2_printf("DML: support: SourceFormatPixelAndScanSupport = %d\n", support->SourceFormatPixelAndS… in dml2_core_utils_print_mode_support_info() 81 if (!fail_only || support->ViewportSizeSupport == 0) in dml2_core_utils_print_mode_support_info() 82 dml2_printf("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport); in dml2_core_utils_print_mode_support_info() 83 if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1) in dml2_core_utils_print_mode_support_info() 84 …dml2_printf("DML: support: LinkRateDoesNotMatchDPVersion = %d\n", support->LinkRateDoesNotMatchDPV… in dml2_core_utils_print_mode_support_info() [all …]
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D | dml2_core_dcn4.c | 1 // SPDX-License-Identifier: MIT 82 ip_caps->pipe_count = ip_params->max_num_dpp; in patch_ip_caps_with_explicit_ip_params() 83 ip_caps->otg_count = ip_params->max_num_otg; in patch_ip_caps_with_explicit_ip_params() 84 ip_caps->num_dsc = ip_params->num_dsc; in patch_ip_caps_with_explicit_ip_params() 85 ip_caps->max_num_dp2p0_streams = ip_params->max_num_dp2p0_streams; in patch_ip_caps_with_explicit_ip_params() 86 ip_caps->max_num_dp2p0_outputs = ip_params->max_num_dp2p0_outputs; in patch_ip_caps_with_explicit_ip_params() 87 ip_caps->max_num_hdmi_frl_outputs = ip_params->max_num_hdmi_frl_outputs; in patch_ip_caps_with_explicit_ip_params() 88 ip_caps->rob_buffer_size_kbytes = ip_params->rob_buffer_size_kbytes; in patch_ip_caps_with_explicit_ip_params() 89 ip_caps->config_return_buffer_size_in_kbytes = ip_params->config_return_buffer_size_in_kbytes; in patch_ip_caps_with_explicit_ip_params() 90 …ip_caps->config_return_buffer_segment_size_in_kbytes = ip_params->config_return_buffer_segment_siz… in patch_ip_caps_with_explicit_ip_params() [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/hwss/dcn10/ |
D | dcn10_hwseq.c | 67 hws->ctx 69 hws->regs->reg 73 hws->shifts->field_name, hws->masks->field_name 88 const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000; in print_microsec() 106 for (i = 0; i < dc->res_pool->pipe_count; i++) { in dcn10_lock_all_pipes() 107 old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes() 108 pipe_ctx = &context->res_ctx.pipe_ctx[i]; in dcn10_lock_all_pipes() 109 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes() 115 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes() 116 !pipe_ctx->stream || in dcn10_lock_all_pipes() [all …]
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/linux-6.12.1/arch/arm64/boot/dts/freescale/ |
D | fsl-ls1046a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1046A family SoC. 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/gpio/gpio.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 37 #address-cells = <1>; [all …]
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D | fsl-ls1088a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1088A family SoC. 5 * Copyright 2017-2020 NXP 10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/thermal/thermal.h> 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 26 #address-cells = <1>; [all …]
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D | fsl-ls208xa.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 6 * Copyright 2017-2020 NXP 12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 13 #include <dt-bindings/thermal/thermal.h> 14 #include <dt-bindings/interrupt-controller/arm-gic.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 32 #address-cells = <1>; [all …]
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D | fsl-ls1043a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for NXP Layerscape-1043A family SoC. 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 12 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #include <dt-bindings/gpio/gpio.h> 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; [all …]
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/linux-6.12.1/drivers/gpu/drm/amd/display/dc/inc/hw/ |
D | transform.h | 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 157 struct rect viewport; member 204 uint32_t num);
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/linux-6.12.1/arch/arm64/boot/dts/toshiba/ |
D | tmpv7708.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 * (C) Copyright 2018 - 2020, Toshiba Corporation. 10 #include <dt-bindings/clock/toshiba,tmpv770x.h> 11 #include <dt-bindings/interrupt-controller/irq.h> 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */ 18 #address-cells = <2>; 19 #size-cells = <2>; 22 #address-cells = <1>; 23 #size-cells = <0>; [all …]
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/linux-6.12.1/arch/arm64/boot/dts/nvidia/ |
D | tegra234.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 3 #include <dt-bindings/clock/tegra234-clock.h> 4 #include <dt-bindings/gpio/tegra234-gpio.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/mailbox/tegra186-hsp.h> 7 #include <dt-bindings/memory/tegra234-mc.h> 8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 9 #include <dt-bindings/power/tegra234-powergate.h> 10 #include <dt-bindings/reset/tegra234-reset.h> 11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h> [all …]
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