bindings/pci/fsl%2Clayerscape-pcie.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Frank Li <Frank.Li@nxp.com>
16   which is used to describe the PLL settings at the time of chip-reset.
26       - enum:
27           - fsl,ls1012a-pcie
28           - fsl,ls1021a-pcie
29           - fsl,ls1028a-pcie
30           - fsl,ls1043a-pcie
31           - fsl,ls1046a-pcie
32           - fsl,ls1088a-pcie
33           - fsl,ls2080a-pcie
34           - fsl,ls2085a-pcie
35           - fsl,ls2088a-pcie
36       - items:
37           - const: fsl,lx2160ar2-pcie
38           - const: fsl,ls2088a-pcie
42   reg-names:
44       - const: regs
45       - const: config
47   fsl,pcie-scfg:
48     $ref: /schemas/types.yaml#/definitions/phandle-array
54         - description: A phandle to the SCFG device node
55         - description: PCIe controller index starting from '0'
58   big-endian:
60     description: If the PEX_LUT and PF register block is in big-endian, specify
63   dma-coherent: true
65   msi-parent: true
67   iommu-map: true
73   interrupt-names:
77   num-viewport:
86   - compatible
87   - reg
88   - reg-names
89   - "#address-cells"
90   - "#size-cells"
91   - device_type
92   - bus-range
93   - ranges
94   - interrupts
95   - interrupt-names
96   - "#interrupt-cells"
97   - interrupt-map-mask
98   - interrupt-map
101   - $ref: /schemas/pci/pci-bus.yaml#
103   - if:
107             - fsl,ls1028a-pcie
108             - fsl,ls1046a-pcie
109             - fsl,ls1043a-pcie
110             - fsl,ls1012a-pcie
115         interrupt-names:
117             - const: pme
118             - const: aer
120   - if:
124             - fsl,ls2080a-pcie
125             - fsl,ls2085a-pcie
126             - fsl,ls2088a-pcie
131         interrupt-names:
133             - const: intr
135   - if:
139             - fsl,ls1088a-pcie
144         interrupt-names:
146             - const: aer
151   - |
152     #include <dt-bindings/interrupt-controller/arm-gic.h>
155       #address-cells = <2>;
156       #size-cells = <2>;
159         compatible = "fsl,ls1088a-pcie";
162         reg-names = "regs", "config";
164         interrupt-names = "aer";
165         #address-cells = <3>;
166         #size-cells = <2>;
167         dma-coherent;
169         bus-range = <0x0 0xff>;
171 …           0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
172         msi-parent = <&its>;
173         #interrupt-cells = <1>;
174         interrupt-map-mask = <0 0 0 7>;
175         interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
179         iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */