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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dintel,ixp4xx-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-ethernet.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Linus Walleij <linus.walleij@linaro.org>
17 The Intel IXP4xx ethernet makes use of the IXP4xx NPE (Network
24 const: intel,ixp4xx-ethernet
30 queue-rx:
31 $ref: /schemas/types.yaml#/definitions/phandle-array
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Dintel,ixp4xx-hss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/intel,ixp4xx-hss.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP4xx HSS makes use of the IXP4xx NPE (Network
20 const: intel,ixp4xx-hss
26 intel,npe-handle:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
30 - description: phandle to the NPE this HSS instance is using
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/linux-6.12.1/Documentation/devicetree/bindings/crypto/
Dintel,ixp4xx-crypto.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
14 The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
16 it is defined as a subnode of the NPE, if crypto support is
21 const: intel,ixp4xx-crypto
23 intel,npe-handle:
24 $ref: /schemas/types.yaml#/definitions/phandle-array
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/linux-6.12.1/arch/arm/boot/dts/intel/ixp/
Dintel-ixp4xx.dtsi1 // SPDX-License-Identifier: ISC
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/gpio/gpio.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
14 compatible = "simple-bus";
15 interrupt-parent = <&intcon>;
22 /* compatible and reg filled in by per-soc device tree */
23 native-endian;
24 #address-cells = <2>;
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Dintel-ixp43x-kixrp435.dts1 // SPDX-License-Identifier: ISC
7 /dts-v1/;
9 #include "intel-ixp43x.dtsi"
10 #include "intel-ixp4xx-reference-design.dtsi"
11 #include <dt-bindings/input/input.h>
16 #address-cells = <1>;
17 #size-cells = <1>;
22 compatible = "intel,ixp4xx-flash", "cfi-flash";
23 bank-width = <2>;
25 intel,ixp4xx-eb-write-enable = <1>;
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Dintel-ixp43x-gateworks-gw2358.dts1 // SPDX-License-Identifier: ISC
3 * Device Tree file for Gateworks IXP43x-based Cambria GW2358
6 /dts-v1/;
8 #include "intel-ixp43x.dtsi"
13 #address-cells = <1>;
14 #size-cells = <1>;
24 stdout-path = "uart0:115200n8";
32 compatible = "gpio-leds";
33 led-user {
36 default-state = "on";
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Dintel-ixp42x-goramo-multilink.dts1 // SPDX-License-Identifier: ISC
5 * - MultiLink Basic (a box)
6 * - MultiLink Max (19" rack mount)
9 * This is one of the few devices supporting the IXP4xx High-Speed Serial
14 /dts-v1/;
16 #include "intel-ixp42x.dtsi"
17 #include <dt-bindings/input/input.h>
21 compatible = "goramo,multilink-router", "intel,ixp42x";
22 #address-cells = <1>;
23 #size-cells = <1>;
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/linux-6.12.1/Documentation/devicetree/bindings/firmware/
Dintel,ixp4xx-network-processing-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/firmware/intel,ixp4xx-network-processing-engine.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Linus Walleij <linus.walleij@linaro.org>
14 On the IXP4xx SoCs, the Network Processing Engine (NPE) is a small
24 - items:
25 - const: intel,ixp4xx-network-processing-engine
29 - description: NPE0 (NPE-A) register range
30 - description: NPE1 (NPE-B) register range
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/linux-6.12.1/drivers/net/ethernet/xscale/
Dixp4xx_eth.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * NPE 0 (NPE-A) 1 (NPE-B) 2 (NPE-C)
13 * RX-free queue 26 27 28
14 * TX-done queue is always 31, per-port RX and TX-ready queues are configurable
17 * bits 0 -> 1 - NPE ID (RX and TX-done)
18 * bits 0 -> 2 - priority (TX, per 802.1D)
19 * bits 3 -> 4 - port ID (user-set?)
20 * bits 5 -> 31 - physical descriptor address
24 #include <linux/dma-mapping.h>
39 #include <linux/soc/ixp4xx/npe.h>
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/linux-6.12.1/drivers/net/wan/
Dixp4xx_hss.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2008 Krzysztof Hałasa <khc@pm.waw.pl>
13 #include <linux/dma-mapping.h>
26 #include <linux/soc/ixp4xx/npe.h>
51 #define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
90 #define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
116 /* Invert data between NPE and HSS FIFOs? (default = no) */
142 /* 56k data endiannes - which bit unused: high (default) or low */
180 * The clock sequence consists of (C - B) states of 0s and 1s, each state is
192 * The sequence takes (C - B) * A + (B + 1) * (A + 1) = 5 * 2 + 3 * 3 bits
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/linux-6.12.1/drivers/crypto/intel/ixp4xx/
Dixp4xx_crypto.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel IXP4xx NPE-C crypto driver
9 #include <linux/dma-mapping.h>
31 #include <linux/soc/ixp4xx/npe.h>
34 /* Intermittent includes, delete this after v5.14-rc1 */
136 u32 crypto_ctx; /* NPE Crypto Param structure address */
223 static struct npe *npe_c;
239 return crypt_phys + (virt - crypt_virt) * sizeof(struct crypt_ctl); in crypt_virt2phys()
244 return crypt_virt + (phys - crypt_phys) / sizeof(struct crypt_ctl); in crypt_phys2virt()
249 return container_of(tfm->__crt_alg, struct ixp_alg, crypto.base)->cfg_enc; in cipher_cfg_enc()
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/linux-6.12.1/drivers/edac/
Dedac_pci_sysfs.c23 static int edac_pci_log_npe = 1; /* log PCI non-parity error errors */
61 return sprintf(data, "%u\n", atomic_read(&pci->counters.pe_count)); in instance_pe_count_show()
67 return sprintf(data, "%u\n", atomic_read(&pci->counters.npe_count)); in instance_npe_count_show()
103 if (instance_attr->show) in edac_pci_instance_show()
104 return instance_attr->show(pci, buffer); in edac_pci_instance_show()
105 return -EIO; in edac_pci_instance_show()
116 if (instance_attr->store) in edac_pci_instance_store()
117 return instance_attr->store(pci, buffer, count); in edac_pci_instance_store()
118 return -EIO; in edac_pci_instance_store()
170 err = -ENODEV; in edac_pci_create_instance_kobj()
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