intel/ixp/intel-ixp42x-goramo-multilink.dts

1 // SPDX-License-Identifier: ISC
5  * - MultiLink Basic (a box)
6  * - MultiLink Max (19" rack mount)
9  * This is one of the few devices supporting the IXP4xx High-Speed Serial
14 /dts-v1/;
16 #include "intel-ixp42x.dtsi"
17 #include <dt-bindings/input/input.h>
21 	compatible = "goramo,multilink-router", "intel,ixp42x";
22 	#address-cells = <1>;
23 	#size-cells = <1>;
36 		stdout-path = "uart0:115200n8";
47 	 * - Create device tree bindings for this as GPIO expander
48 	 * - Write a pure DT GPIO driver using these bindings
49 	 * - Support cascading in the style of gpio-74x164.c (cannot be reused, very different)
51 	gpio_74: gpio-74hc4094 {
53 		cp-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
54 		d-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
55 		str-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
56 		/* oe-gpios is optional */
57 		gpio-controller;
58 		#gpio-cells = <2>;
60 		registers-number = <1>;
61 		gpio-line-names = "CONTROL_HSS0_CLK_INT", "CONTROL_HSS1_CLK_INT", "CONTROL_HSS0_DTR_N",
69 				compatible = "intel,ixp4xx-flash", "cfi-flash";
70 				bank-width = <2>;
72 				intel,ixp4xx-eb-write-enable = <1>;
77 					compatible = "redboot-fis";
79 					fis-index-block = <0x7f>;
92 			#interrupt-cells = <1>;
93 			interrupt-map-mask = <0xf800 0 0 7>;
94 			interrupt-map =
95 			/* IDSEL 11 - Ethernet A */
100 			/* IDSEL 12 - Ethernet B */
105 			/* IDSEL 13 - MPCI */
110 			/* IDSEL 14 - NEC */
118 		npe@c8006000 {
121 				intel,queue-chl-rxtrig = <&qmgr 12>;
122 				intel,queue-chl-txready = <&qmgr 34>;
123 				intel,queue-pkt-rx = <&qmgr 13>;
124 				intel,queue-pkt-tx = <&qmgr 14>, <&qmgr 15>, <&qmgr 16>, <&qmgr 17>;
125 				intel,queue-pkt-rxfree = <&qmgr 18>, <&qmgr 19>, <&qmgr 20>, <&qmgr 21>;
126 				intel,queue-pkt-txdone = <&qmgr 22>;
127 				/* The Goramo GPIO-based clock etc control */
128 				cts-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
129 				rts-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
130 				dcd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
131 				dtr-gpios = <&gpio_74 2 GPIO_ACTIVE_LOW>;
132 				clk-internal-gpios = <&gpio_74 0 GPIO_ACTIVE_HIGH>;
136 				intel,queue-chl-rxtrig = <&qmgr 10>;
137 				intel,queue-chl-txready = <&qmgr 35>;
138 				intel,queue-pkt-rx = <&qmgr 0>;
139 				intel,queue-pkt-tx = <&qmgr 5>, <&qmgr 6>, <&qmgr 7>, <&qmgr 8>;
140 				intel,queue-pkt-rxfree = <&qmgr 1>, <&qmgr 2>, <&qmgr 3>, <&qmgr 4>;
141 				intel,queue-pkt-txdone = <&qmgr 9>;
142 				/* The Goramo GPIO-based clock etc control */
143 				cts-gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
144 				rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
145 				dcd-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
146 				dtr-gpios = <&gpio_74 3 GPIO_ACTIVE_LOW>;
147 				clk-internal-gpios = <&gpio_74 1 GPIO_ACTIVE_HIGH>;
154 			queue-rx = <&qmgr 3>;
155 			queue-txready = <&qmgr 32>;
156 			phy-mode = "rgmii";
157 			phy-handle = <&phy0>;
160 				#address-cells = <1>;
161 				#size-cells = <0>;
163 				phy0: ethernet-phy@0 {
167 				phy1: ethernet-phy@1 {
176 			queue-rx = <&qmgr 4>;
177 			queue-txready = <&qmgr 33>;
178 			phy-mode = "rgmii";
179 			phy-handle = <&phy1>;