| /linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/ |
| D | al,alpine-msix.txt | 3 See arm,gic-v3.txt for SPI and MSI definitions.
7 - compatible: should be "al,alpine-msix"
8 - reg: physical base address and size of the registers
9 - interrupt-controller: identifies the node as an interrupt controller
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
18 compatible = "al,alpine-msix";
20 interrupt-parent = <&gic>;
21 interrupt-controller;
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| D | marvell,odmi-controller.txt | 2 * Marvell ODMI for MSI support
4 Some Marvell SoCs have an On-Die Message Interrupt (ODMI) controller
5 which can be used by on-board peripheral for MSI interrupts.
9 - compatible : The value here should contain:
11 "marvell,ap806-odmi-controller", "marvell,odmi-controller".
13 - interrupt,controller : Identifies the node as an interrupt controller.
15 - msi-controller : Identifies the node as an MSI controller.
17 - marvell,odmi-frames : Number of ODMI frames available. Each frame
20 - reg : List of register definitions, one for each
23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
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| D | arm,gic.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <marc.zyngier@arm.com>
14 interrupts (PPI), shared processor interrupts (SPI) and software
22 - $ref: /schemas/interrupt-controller.yaml#
27 - items:
28 - enum:
29 - arm,arm11mp-gic
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| D | arm,gic-v3.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marc Zyngier <maz@kernel.org>
14 Peripheral Interrupts (PPI), Shared Peripheral Interrupts (SPI),
15 Software Generated Interrupts (SGI), and Locality-specific Peripheral
19 - $ref: /schemas/interrupt-controller.yaml#
24 - items:
25 - enum:
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| /linux-6.12.1/drivers/irqchip/ |
| D | irq-gic-v2m.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * ARM GIC v2m MSI(-X) support
21 #include <linux/msi.h>
26 #include <linux/irqchip/arm-gic.h>
27 #include <linux/irqchip/arm-gic-common.h>
29 #include "irq-msi-lib.h"
34 * [25:16] lowest SPI assigned to MSI
36 * [9:0] Numer of SPIs assigned to MSI
52 /* APM X-Gene with GICv2m MSI_IIDR register value */
69 void __iomem *base; /* GICv2m virt address */ member
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| D | irq-mvebu-icu.c | 5 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
18 #include <linux/msi.h>
23 #include "irq-msi-lib.h"
25 #include <dt-bindings/interrupt-controller/mvebu-icu.h>
55 void __iomem *base; member
71 struct mvebu_icu_msi_data *msi_data = d->host_data; in mvebu_icu_translate()
72 struct mvebu_icu *icu = msi_data->icu; in mvebu_icu_translate()
75 if (WARN_ON(fwspec->param_count != param_count)) { in mvebu_icu_translate()
76 dev_err(icu->dev, "wrong ICU parameter count %d\n", in mvebu_icu_translate()
77 fwspec->param_count); in mvebu_icu_translate()
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| D | irq-mvebu-odmi.c | 4 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #define pr_fmt(fmt) "GIC-ODMI: " fmt
17 #include <linux/msi.h>
21 #include "irq-msi-lib.h"
23 #include <dt-bindings/interrupt-controller/arm-gic.h>
38 #define NODMIS_MASK (NODMIS_PER_FRAME - 1)
42 void __iomem *base; member
59 if (WARN_ON(d->hwirq >= odmis_count * NODMIS_PER_FRAME)) in odmi_compose_msi_msg()
62 odmi = &odmis[d->hwirq >> NODMIS_SHIFT]; in odmi_compose_msi_msg()
63 odmin = d->hwirq & NODMIS_MASK; in odmi_compose_msi_msg()
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| D | irq-mvebu-sei.c | 1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "mvebu-sei: " fmt
11 #include <linux/msi.h>
17 #include "irq-msi-lib.h"
43 void __iomem *base; member
50 /* Lock on MSI allocations/releases */
61 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq()
63 writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)), in mvebu_sei_ack_irq()
64 sei->base + GICP_SECR(reg_idx)); in mvebu_sei_ack_irq()
70 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq()
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| D | irq-alpine-msi.c | 6 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 #include <linux/irqchip/arm-gic.h>
17 #include <linux/msi.h>
26 #include <asm/msi.h>
63 spin_lock(&priv->msi_map_lock); in alpine_msix_allocate_sgi()
65 first = bitmap_find_next_zero_area(priv->msi_map, priv->num_spis, 0, in alpine_msix_allocate_sgi()
67 if (first >= priv->num_spis) { in alpine_msix_allocate_sgi()
68 spin_unlock(&priv->msi_map_lock); in alpine_msix_allocate_sgi()
69 return -ENOSPC; in alpine_msix_allocate_sgi()
72 bitmap_set(priv->msi_map, first, num_req); in alpine_msix_allocate_sgi()
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| /linux-6.12.1/arch/arm64/boot/dts/marvell/ |
| D | armada-ap80x.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
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| /linux-6.12.1/drivers/spi/ |
| D | spi-pci1xxxx.c | 1 // SPDX-License-Identifier: GPL-2.0
2 // PCI1xxxx SPI driver
10 #include <linux/dma-mapping.h>
14 #include <linux/msi.h>
18 #include <linux/spi/spi.h>
21 #define DRV_NAME "spi-pci1xxxx"
105 /* x refers to SPI Host Controller HW instance id in the below macros - 0 or 1 */
197 writel(SPI_SYSLOCK, par->reg_base + SPI_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
198 return readl(par->reg_base + SPI_SYSLOCK_REG); in pci1xxxx_set_sys_lock()
212 writel(0x0, par->reg_base + SPI_SYSLOCK_REG); in pci1xxxx_release_sys_lock()
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| /linux-6.12.1/arch/arm64/boot/dts/broadcom/northstar2/ |
| D | ns2.dtsi | 35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
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| /linux-6.12.1/arch/arm/boot/dts/amazon/ |
| D | alpine.dtsi | 27 #include <dt-bindings/interrupt-controller/arm-gic.h>
30 #address-cells = <2>;
31 #size-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "al,alpine-smp";
47 compatible = "arm,cortex-a15";
50 clock-frequency = <1700000000>;
54 compatible = "arm,cortex-a15";
57 clock-frequency = <1700000000>;
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| /linux-6.12.1/arch/arm64/boot/dts/amazon/ |
| D | alpine-v2.dtsi | 4 * Antoine Tenart <antoine.tenart@free-electrons.com>
16 * - Redistributions of source code must retain the above
20 * - Redistributions in binary form must reproduce the above
35 /dts-v1/;
37 #include <dt-bindings/interrupt-controller/arm-gic.h>
41 compatible = "al,alpine-v2";
42 interrupt-parent = <&gic>;
43 #address-cells = <2>;
44 #size-cells = <2>;
47 #address-cells = <2>;
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| D | alpine-v3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 compatible = "amazon,al-alpine-v3";
14 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a72";
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| /linux-6.12.1/arch/riscv/boot/dts/sifive/ |
| D | fu740-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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| /linux-6.12.1/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls1088a.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
5 * Copyright 2017-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
26 #address-cells = <1>;
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| D | fsl-ls208xa.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6 * Copyright 2017-2020 NXP
12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
32 #address-cells = <1>;
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| /linux-6.12.1/drivers/media/pci/ddbridge/ |
| D | ddbridge.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2010-2017 Digital Devices GmbH
31 #include <linux/spi/spi.h>
50 #define DDBRIDGE_VERSION "0.9.33-integrated"
62 u32 base; member
315 int msi; member
354 /* ddbridge-core.c */
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| /linux-6.12.1/Documentation/devicetree/bindings/pci/ |
| D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
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| /linux-6.12.1/drivers/pci/controller/ |
| D | pci-aardvark.c | 1 // SPDX-License-Identifier: GPL-2.0
20 #include <linux/pci-ecam.h>
24 #include <linux/msi.h>
29 #include "../pci-bridge-emul.h"
43 /* PIO registers base address and register offsets */
139 #define OB_WIN_DEFAULT_ACTIONS (OB_WIN_ACTIONS(OB_WIN_COUNT-1) + 0x4)
164 /* LMI registers base address and register offsets */
269 void __iomem *base; member
294 writel(val, pcie->base + reg); in advk_writel()
299 return readl(pcie->base + reg); in advk_readl()
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| /linux-6.12.1/drivers/acpi/arm64/ |
| D | iort.c | 1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/dma-map-ops.h>
45 * iort_set_fwnode() - Create iort_fwnode and use it to register
62 return -ENOMEM; in iort_set_fwnode()
64 INIT_LIST_HEAD(&np->list); in iort_set_fwnode()
65 np->iort_node = iort_node; in iort_set_fwnode()
66 np->fwnode = fwnode; in iort_set_fwnode()
69 list_add_tail(&np->list, &iort_fwnode_list); in iort_set_fwnode()
76 * iort_get_fwnode() - Retrieve fwnode associated with an IORT node
78 * @node: IORT table node to be looked-up
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| /linux-6.12.1/arch/riscv/boot/dts/starfive/ |
| D | jh7110.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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| /linux-6.12.1/drivers/mfd/ |
| D | timberdale.c | 1 // SPDX-License-Identifier: GPL-2.0-only
21 #include <linux/platform_data/i2c-ocores.h>
22 #include <linux/platform_data/i2c-xiic.h>
24 #include <linux/spi/spi.h>
25 #include <linux/spi/xilinx_spi.h>
26 #include <linux/spi/max7301.h>
27 #include <linux/spi/mc33880.h>
50 /*--------------------------------------------------------------------------*/
53 PROPERTY_ENTRY_U32("ti,x-plate-ohms", 100),
111 .base = 200
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| /linux-6.12.1/drivers/net/ethernet/intel/iavf/ |
| D | iavf_ethtool.c | 1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
13 * struct iavf_stats - definition for an ethtool statistic
14 * @stat_string: statistic name to display in ethtool -S output
16 * @stat_offset: offsetof() the stat from a base pointer
19 * It defines a statistic as offset from a common base pointer. Stats should
56 IAVF_QUEUE_STAT("%s-%u.packets", stats.packets),
57 IAVF_QUEUE_STAT("%s-%u.bytes", stats.bytes),
61 * iavf_add_one_ethtool_stat - copy the stat into the supplied buffer
84 p = (char *)pointer + stat->stat_offset; in iavf_add_one_ethtool_stat()
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