4  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
11 #define pr_fmt(fmt) "GIC-ODMI: " fmt
17 #include <linux/msi.h>
21 #include "irq-msi-lib.h"
23 #include <dt-bindings/interrupt-controller/arm-gic.h>
38 #define NODMIS_MASK		(NODMIS_PER_FRAME - 1)
42 	void __iomem *base;  member
59 	if (WARN_ON(d->hwirq >= odmis_count * NODMIS_PER_FRAME))  in odmi_compose_msi_msg()
62 	odmi = &odmis[d->hwirq >> NODMIS_SHIFT];  in odmi_compose_msi_msg()
63 	odmin = d->hwirq & NODMIS_MASK;  in odmi_compose_msi_msg()
65 	addr = odmi->res.start + GICP_ODMIN_SET;  in odmi_compose_msi_msg()
67 	msg->address_hi = upper_32_bits(addr);  in odmi_compose_msi_msg()
68 	msg->address_lo = lower_32_bits(addr);  in odmi_compose_msi_msg()
69 	msg->data = odmin << GICP_ODMI_INT_NUM_SHIFT;  in odmi_compose_msi_msg()
94 		return -ENOSPC;  in odmi_irq_domain_alloc()
103 	fwspec.fwnode = domain->parent->fwnode;  in odmi_irq_domain_alloc()
106 	fwspec.param[1] = odmi->spi_base - 32 + odmin;  in odmi_irq_domain_alloc()
119 	d = irq_domain_get_irq_data(domain->parent, virq);  in odmi_irq_domain_alloc()
120 	d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);  in odmi_irq_domain_alloc()
133 	if (d->hwirq >= odmis_count * NODMIS_PER_FRAME) {  in odmi_irq_domain_free()
134 		pr_err("Failed to teardown msi. Invalid hwirq %lu\n", d->hwirq);  in odmi_irq_domain_free()
140 	/* Actually free the MSI */  in odmi_irq_domain_free()
142 	__clear_bit(d->hwirq, odmis_bm);  in odmi_irq_domain_free()
162 	.prefix			= "ODMI-",
172 	if (of_property_read_u32(node, "marvell,odmi-frames", &odmis_count))  in mvebu_odmi_init()
173 		return -EINVAL;  in mvebu_odmi_init()
177 		return -ENOMEM;  in mvebu_odmi_init()
181 		ret = -ENOMEM;  in mvebu_odmi_init()
188 		ret = of_address_to_resource(node, i, &odmi->res);  in mvebu_odmi_init()
192 		odmi->base = of_io_request_and_map(node, i, "odmi");  in mvebu_odmi_init()
193 		if (IS_ERR(odmi->base)) {  in mvebu_odmi_init()
194 			ret = PTR_ERR(odmi->base);  in mvebu_odmi_init()
198 		if (of_property_read_u32_index(node, "marvell,spi-base",  in mvebu_odmi_init()
199 					       i, &odmi->spi_base)) {  in mvebu_odmi_init()
200 			ret = -EINVAL;  in mvebu_odmi_init()
212 		ret = -ENOMEM;  in mvebu_odmi_init()
217 	inner_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT;  in mvebu_odmi_init()
218 	inner_domain->msi_parent_ops = &odmi_msi_parent_ops;  in mvebu_odmi_init()
226 		if (odmi->base && !IS_ERR(odmi->base))  in mvebu_odmi_init()
227 			iounmap(odmis[i].base);  in mvebu_odmi_init()
235 IRQCHIP_DECLARE(mvebu_odmi, "marvell,odmi-controller", mvebu_odmi_init);