Searched +full:msc313 +full:- +full:cpupll (Results 1 – 4 of 4) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/clock/mstar,msc313-cpupll.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#7 title: MStar/Sigmastar MSC313 CPU PLL10 - Daniel Palmer <daniel@thingy.jp>13 The MStar/SigmaStar MSC313 and later ARMv7 chips have a scalable18 const: mstar,msc313-cpupll20 "#clock-cells":30 - compatible[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later7 #include <dt-bindings/interrupt-controller/irq.h>8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/clock/mstar-msc313-mpll.h>12 #address-cells = <1>;13 #size-cells = <1>;14 interrupt-parent = <&gic>;17 #address-cells = <1>;18 #size-cells = <0>;22 compatible = "arm,cortex-a7";[all …]
1 // SPDX-License-Identifier: GPL-2.06 #include <linux/clk-provider.h>17 * 0x140 -- LPF low. Seems to store one half of the clock transition19 * 0x148 -- LPF high. Seems to store one half of the clock transition21 * 0x150 -- vendor code says "toggle lpf enable"22 * 0x154 -- mu?23 * 0x15c -- lpf_update_count?24 * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank?25 * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to27 * 0x174 -- Seems to be the PLL lock status bit[all …]
1 # SPDX-License-Identifier: GPL-2.06 obj-$(CONFIG_MSTAR_MSC313_CPUPLL) += clk-msc313-cpupll.o7 obj-$(CONFIG_MSTAR_MSC313_MPLL) += clk-msc313-mpll.o