Lines Matching +full:msc313 +full:- +full:cpupll

1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
17 * 0x140 -- LPF low. Seems to store one half of the clock transition
19 * 0x148 -- LPF high. Seems to store one half of the clock transition
21 * 0x150 -- vendor code says "toggle lpf enable"
22 * 0x154 -- mu?
23 * 0x15c -- lpf_update_count?
24 * 0x160 -- vendor code says "switch to LPF". Clock source config? Register bank?
25 * 0x164 -- vendor code says "from low to high" which seems to mean transition from LPF low to
27 * 0x174 -- Seems to be the PLL lock status bit
28 * 0x180 -- Seems to be the current frequency, this might need to be populated by software?
38 * frequency - register value
40 * 400000000 - 0x0067AE14
41 * 600000000 - 0x00451EB8,
42 * 800000000 - 0x0033D70A,
43 * 1000000000 - 0x002978d4,
71 static u32 msc313_cpupll_reg_read32(struct msc313_cpupll *cpupll, unsigned int reg) in msc313_cpupll_reg_read32() argument
75 value = ioread16(cpupll->base + reg + 4) << 16; in msc313_cpupll_reg_read32()
76 value |= ioread16(cpupll->base + reg); in msc313_cpupll_reg_read32()
81 static void msc313_cpupll_reg_write32(struct msc313_cpupll *cpupll, unsigned int reg, u32 value) in msc313_cpupll_reg_write32() argument
85 iowrite16(l, cpupll->base + reg); in msc313_cpupll_reg_write32()
86 iowrite16(h, cpupll->base + reg + 4); in msc313_cpupll_reg_write32()
89 static void msc313_cpupll_setfreq(struct msc313_cpupll *cpupll, u32 regvalue) in msc313_cpupll_setfreq() argument
93 msc313_cpupll_reg_write32(cpupll, REG_LPF_HIGH_BOTTOM, regvalue); in msc313_cpupll_setfreq()
95 iowrite16(0x1, cpupll->base + REG_LPF_MYSTERYONE); in msc313_cpupll_setfreq()
96 iowrite16(0x6, cpupll->base + REG_LPF_MYSTERYTWO); in msc313_cpupll_setfreq()
97 iowrite16(0x8, cpupll->base + REG_LPF_UPDATE_COUNT); in msc313_cpupll_setfreq()
98 iowrite16(BIT(12), cpupll->base + REG_LPF_TRANSITIONCTRL); in msc313_cpupll_setfreq()
100 iowrite16(0, cpupll->base + REG_LPF_TOGGLE); in msc313_cpupll_setfreq()
101 iowrite16(1, cpupll->base + REG_LPF_TOGGLE); in msc313_cpupll_setfreq()
104 while (!(ioread16(cpupll->base + REG_LPF_LOCK))) { in msc313_cpupll_setfreq()
112 iowrite16(0, cpupll->base + REG_LPF_TOGGLE); in msc313_cpupll_setfreq()
114 msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L, regvalue); in msc313_cpupll_setfreq()
137 struct msc313_cpupll *cpupll = to_cpupll(hw); in msc313_cpupll_recalc_rate() local
139 return msc313_cpupll_frequencyforreg(msc313_cpupll_reg_read32(cpupll, REG_LPF_LOW_L), in msc313_cpupll_recalc_rate()
153 for (; rounded >= rate && reg > 0; reg--) in msc313_cpupll_round_rate()
161 struct msc313_cpupll *cpupll = to_cpupll(hw); in msc313_cpupll_set_rate() local
164 msc313_cpupll_setfreq(cpupll, reg); in msc313_cpupll_set_rate()
176 { .compatible = "mstar,msc313-cpupll" },
184 struct device *dev = &pdev->dev; in msc313_cpupll_probe()
185 struct msc313_cpupll *cpupll; in msc313_cpupll_probe() local
188 cpupll = devm_kzalloc(&pdev->dev, sizeof(*cpupll), GFP_KERNEL); in msc313_cpupll_probe()
189 if (!cpupll) in msc313_cpupll_probe()
190 return -ENOMEM; in msc313_cpupll_probe()
192 cpupll->base = devm_platform_ioremap_resource(pdev, 0); in msc313_cpupll_probe()
193 if (IS_ERR(cpupll->base)) in msc313_cpupll_probe()
194 return PTR_ERR(cpupll->base); in msc313_cpupll_probe()
197 msc313_cpupll_reg_write32(cpupll, REG_LPF_LOW_L, in msc313_cpupll_probe()
198 msc313_cpupll_reg_read32(cpupll, REG_CURRENT)); in msc313_cpupll_probe()
204 cpupll->clk_hw.init = &clk_init; in msc313_cpupll_probe()
206 ret = devm_clk_hw_register(dev, &cpupll->clk_hw); in msc313_cpupll_probe()
210 return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get, &cpupll->clk_hw); in msc313_cpupll_probe()
215 .name = "mstar-msc313-cpupll",