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/linux-6.12.1/drivers/net/mdio/
DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # MDIO Layer Configuration
7 tristate "MDIO bus device drivers"
9 MDIO devices and driver infrastructure code.
20 loadable module or built-in.
27 FWNODE MDIO bus (Ethernet PHY) accessors
35 OpenFirmware MDIO bus (Ethernet PHY) accessors
42 ACPI MDIO bus (Ethernet PHY) accessors
50 tristate "Allwinner sun4i MDIO interface support"
53 This driver supports the MDIO interface found in the network
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Dmdio-mux-multiplexer.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* MDIO bus multiplexer using kernel multiplexer subsystem
7 #include <linux/mdio-mux.h>
19 * mdio_mux_multiplexer_switch_fn - This function is called by the mdio-mux
20 * layer when it thinks the mdio bus
21 * multiplexer needs to switch.
23 * @desired_child: value of the 'reg' property of the target child MDIO node.
27 * The first time this function is called, current_child == -1.
44 if (s->do_deselect) in mdio_mux_multiplexer_switch_fn()
45 ret = mux_control_deselect(s->muxc); in mdio_mux_multiplexer_switch_fn()
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Dmdio-mux-meson-gxl.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/mdio-mux.h>
59 writel(REG4_PWRUPRSTSIG, priv->regs + ETH_REG4); in gxl_enable_internal_mdio()
60 writel(val, priv->regs + ETH_REG3); in gxl_enable_internal_mdio()
66 * drivers/net/phy/meson-gxl.c to properly match the PHY. in gxl_enable_internal_mdio()
69 priv->regs + ETH_REG2); in gxl_enable_internal_mdio()
73 writel(val, priv->regs + ETH_REG3); in gxl_enable_internal_mdio()
74 writel(0, priv->regs + ETH_REG4); in gxl_enable_internal_mdio()
82 /* Reset the mdio bus mux to the external phy */ in gxl_enable_external_mdio()
83 writel(0, priv->regs + ETH_REG3); in gxl_enable_external_mdio()
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DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 # Makefile for Linux MDIO bus drivers
4 obj-$(CONFIG_ACPI_MDIO) += acpi_mdio.o
5 obj-$(CONFIG_FWNODE_MDIO) += fwnode_mdio.o
6 obj-$(CONFIG_OF_MDIO) += of_mdio.o
8 obj-$(CONFIG_MDIO_ASPEED) += mdio-aspeed.o
9 obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o
10 obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o
11 obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
12 obj-$(CONFIG_MDIO_CAVIUM) += mdio-cavium.o
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Dmdio-mux-gpio.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/mdio-mux.h>
15 #define DRV_DESCRIPTION "GPIO controlled MDIO bus multiplexer driver"
33 gpiod_set_array_value_cansleep(s->gpios->ndescs, s->gpios->desc, in mdio_mux_gpio_switch_fn()
34 s->gpios->info, values); in mdio_mux_gpio_switch_fn()
45 gpios = devm_gpiod_get_array(&pdev->dev, NULL, GPIOD_OUT_LOW); in mdio_mux_gpio_probe()
49 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); in mdio_mux_gpio_probe()
51 return -ENOMEM; in mdio_mux_gpio_probe()
53 s->gpios = gpios; in mdio_mux_gpio_probe()
55 r = mdio_mux_init(&pdev->dev, pdev->dev.of_node, in mdio_mux_gpio_probe()
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Dmdio-mux-meson-g12a.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/clk-provider.h>
13 #include <linux/mdio-mux.h>
75 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_recalc_rate()
85 u32 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
89 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
93 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_enable()
100 return readl_poll_timeout(pll->base + ETH_PLL_CTL0, val, in g12a_ephy_pll_enable()
109 val = readl(pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_disable()
112 writel(val, pll->base + ETH_PLL_CTL0); in g12a_ephy_pll_disable()
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Dmdio-mux-mmioreg.c1 // SPDX-License-Identifier: GPL-2.0
3 * Simple memory-mapped device MDIO MUX driver
11 #include <linux/mdio-mux.h>
26 * MDIO multiplexing switch function
28 * This function is called by the mdio-mux layer when it thinks the mdio bus
29 * multiplexer needs to switch.
32 * s->mask).
34 * 'desired_child' is the value of the 'reg' property of the target child MDIO
37 * The first time this function is called, current_child == -1.
48 void __iomem *p = ioremap(s->phys, s->iosize); in mdio_mux_mmioreg_switch_fn()
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Dmdio-mux.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/mdio-mux.h>
13 #define DRV_DESCRIPTION "MDIO bus multiplexer driver"
40 struct mdio_mux_child_bus *cb = bus->priv; in mdio_mux_read()
41 struct mdio_mux_parent_bus *pb = cb->parent; in mdio_mux_read()
44 mutex_lock_nested(&pb->mii_bus->mdio_lock, MDIO_MUTEX_MUX); in mdio_mux_read()
45 r = pb->switch_fn(pb->current_child, cb->bus_number, pb->switch_data); in mdio_mux_read()
49 pb->current_child = cb->bus_number; in mdio_mux_read()
51 r = pb->mii_bus->read(pb->mii_bus, phy_id, regnum); in mdio_mux_read()
53 mutex_unlock(&pb->mii_bus->mdio_lock); in mdio_mux_read()
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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dmdio-mux-multiplexer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer consumer device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of MDIO mux when MDIO mux is defined as a consumer
19 - $ref: /schemas/net/mdio-mux.yaml#
23 const: mdio-mux-multiplexer
25 mux-controls:
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Dmdio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common MDIO bus multiplexer/switch properties.
10 - Andrew Lunn <andrew@lunn.ch>
13 An MDIO bus multiplexer/switch will have several child busses that are
14 numbered uniquely in a device dependent manner. The nodes for an MDIO
15 bus multiplexer/switch will have one child node for each child bus.
18 mdio-parent-bus:
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Dmdio-mux-mmioreg.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
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Damlogic,g12a-mdio-mux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/amlogic,g12a-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO bus multiplexer/glue of Amlogic G12a SoC family
10 This is a special case of a MDIO bus multiplexer. It allows to choose between
11 the internal mdio bus leading to the embedded 10/100 PHY or the external
12 MDIO bus.
15 - Neil Armstrong <neil.armstrong@linaro.org>
18 - $ref: mdio-mux.yaml#
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Damlogic,gxl-mdio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/amlogic,gxl-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic GXL MDIO bus multiplexer
10 - Jerome Brunet <jbrunet@baylibre.com>
13 This is a special case of a MDIO bus multiplexer. It allows to choose between
14 the internal mdio bus leading to the embedded 10/100 PHY or the external
15 MDIO bus on the Amlogic GXL SoC family.
18 - $ref: mdio-mux.yaml#
[all …]
Dbrcm,bcm6368-mdio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/brcm,bcm6368-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6368 MDIO bus multiplexer
10 - Álvaro Fernández Rojas <noltari@gmail.com>
13 This MDIO bus multiplexer defines buses that could be internal as well as
15 properties as well to generate desired MDIO transaction on appropriate bus.
18 - $ref: mdio-mux.yaml#
22 const: brcm,bcm6368-mdio-mux
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Dbrcm,mdio-mux-iproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/brcm,mdio-mux-iproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO bus multiplexer found in Broadcom iProc based SoCs.
10 - Florian Fainelli <f.fainelli@gmail.com>
13 This MDIO bus multiplexer defines buses that could be internal as well as
14 external to SoCs and could accept MDIO transaction compatible to C-22 or
15 C-45 Clause. When child bus is selected, one needs to select these two
16 properties as well to generate desired MDIO transaction on appropriate bus.
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Dmdio-mux-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. One or more GPIO
17 - $ref: /schemas/net/mdio-mux.yaml#
21 const: mdio-mux-gpio
25 List of GPIOs used to control the multiplexer, least significant bit first.
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/linux-6.12.1/Documentation/devicetree/bindings/mux/
Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
27 mux-reg-masks:
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/linux-6.12.1/include/linux/
Dmdio-mux.h2 * MDIO bus multiplexer framwork.
15 /* mdio_mux_init() - Initialize a MDIO mux
16 * @dev The device owning the MDIO mux
17 * @mux_node The device node of the MDIO mux
18 * @switch_fn The function called for switching target MDIO child
19 * mux_handle A pointer to a (void *) used internaly by mdio-mux
/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dfsl-lx2160a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
Dfsl-lx2162a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2162a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "LTM4619-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
[all …]
/linux-6.12.1/arch/arm64/boot/dts/ti/
Dk3-am642-evm-icssg1-dualemac.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include "k3-pinctrl.h"
16 ethernet1 = "/icssg1-eth/ethernet-ports/port@1";
19 mdio-mux-2 {
20 compatible = "mdio-mux-multiplexer";
21 mux-controls = <&mdio_mux>;
22 mdio-parent-bus = <&icssg1_mdio>;
[all …]
Dk3-am642-evm-icssg1-dualemac-mii.dtso1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include "k3-pinctrl.h"
15 ethernet1 = "/icssg1-eth/ethernet-ports/port@1";
18 mdio-mux-2 {
19 compatible = "mdio-mux-multiplexer";
20 mux-controls = <&mdio_mux>;
21 mdio-parent-bus = <&icssg1_mdio>;
[all …]
/linux-6.12.1/Documentation/networking/dsa/
Dbcm_sf2.rst8 - xDSL gateways such as BCM63138
9 - streaming/multimedia Set Top Box such as BCM7445
10 - Cable Modem/residential gateways such as BCM7145/BCM3390
13 ports, offering a range of built-in and customizable interfaces:
15 - single integrated Gigabit PHY
16 - quad integrated Gigabit PHY
17 - quad external Gigabit PHY w/ MDIO multiplexer
18 - integrated MoCA PHY
19 - several external MII/RevMII/GMII/RGMII interfaces
22 fail-over not to lose packets during a MoCA role re-election, as well as out of
[all …]
/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dqcom,ipq8064-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq8064-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 Top Level Mode Multiplexer pin controller in Qualcomm IPQ8064 SoC.
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,ipq8064-pinctrl
28 gpio-reserved-ranges: true
31 "-state$":
[all …]

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