bindings/pinctrl/qcom%2Cipq8064-pinctrl.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,ipq8064-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Bjorn Andersson <bjorn.andersson@linaro.org>
13   Top Level Mode Multiplexer pin controller in Qualcomm IPQ8064 SoC.
16   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20     const: qcom,ipq8064-pinctrl
28   gpio-reserved-ranges: true
31   "-state$":
33       - $ref: "#/$defs/qcom-ipq8064-tlmm-state"
34       - patternProperties:
35           "-pins$":
36             $ref: "#/$defs/qcom-ipq8064-tlmm-state"
40   qcom-ipq8064-tlmm-state:
45     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
55             - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-8])$"
56             - enum: [ sdc3_clk, sdc3_cmd, sdc3_data ]
64         enum: [ mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
73       - pins
76   - compatible
77   - reg
82   - |
83     #include <dt-bindings/interrupt-controller/arm-gic.h>
85         compatible = "qcom,ipq8064-pinctrl";
88         gpio-controller;
89         #gpio-cells = <2>;
90         gpio-ranges = <&tlmm 0 0 69>;
91         interrupt-controller;
92         #interrupt-cells = <2>;
95         uart-state {
96             rx-pins {
99                 bias-pull-up;
102             tx-pins {
105                 bias-disable;