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/linux-6.12.1/Documentation/devicetree/bindings/net/
Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
25 - st,stm32mp13-dwmac
26 - st,stm32mp25-dwmac
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Dnxp,dwmac-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/nxp,dwmac-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Clark Wang <xiaoning.wang@nxp.com>
11 - Shawn Guo <shawnguo@kernel.org>
12 - NXP Linux Team <linux-imx@nxp.com>
20 - nxp,imx8mp-dwmac-eqos
21 - nxp,imx8dxl-dwmac-eqos
22 - nxp,imx93-dwmac-eqos
[all …]
Dmediatek-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mediatek-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biao Huang <biao.huang@mediatek.com>
21 - mediatek,mt2712-gmac
22 - mediatek,mt8188-gmac
23 - mediatek,mt8195-gmac
25 - compatible
28 - $ref: snps,dwmac.yaml#
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Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
[all …]
Dingenic,mac.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ingenic,mac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MAC in Ingenic SoCs
10 - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
18 - ingenic,jz4775-mac
19 - ingenic,x1000-mac
20 - ingenic,x1600-mac
21 - ingenic,x1830-mac
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Dti,dp83867.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
23 transformer. This device interfaces directly to the MAC layer through the
34 nvmem-cells:
40 nvmem-cell-names:
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Dsti-dwmac.txt10 - compatible : "st,stih407-dwmac"
11 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
13 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
15 - pinctrl-0: pin-control for all the MII mode supported.
18 - resets : phandle pointing to the system reset controller with correct
20 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
21 MAC can generate it.
22 - st,tx-retime-src: This specifies which clk is wired up to the mac for
23 retimeing tx lines. This is totally board dependent and can take one of the
26 - sti-ethclk: this is the phy clock.
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/linux-6.12.1/drivers/net/ethernet/sunplus/
Dspl2sw_driver.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/nvmem-consumer.h>
13 #include <linux/clk.h>
27 struct spl2sw_mac *mac = netdev_priv(ndev); in spl2sw_ethernet_open() local
28 struct spl2sw_common *comm = mac->comm; in spl2sw_ethernet_open()
31 netdev_dbg(ndev, "Open port = %x\n", mac->lan_port); in spl2sw_ethernet_open()
33 comm->enable |= mac->lan_port; in spl2sw_ethernet_open()
37 /* Enable TX and RX interrupts */ in spl2sw_ethernet_open()
38 mask = readl(comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_ethernet_open()
40 writel(mask, comm->l2sw_reg_base + L2SW_SW_INT_MASK_0); in spl2sw_ethernet_open()
[all …]
Dspl2sw_define.h1 /* SPDX-License-Identifier: GPL-2.0 */
9 #define MAX_NETDEV_NUM 2 /* Maximum # of net-device */
21 #define MAC_INT_TX_SOC_PAUSE_ON BIT(15) /* Soc Port TX Pause On */
29 #define MAC_INT_TX_DONE_L BIT(3) /* TX Low Priority Done */
30 #define MAC_INT_TX_DONE_H BIT(2) /* TX High Priority Done */
31 #define MAC_INT_TX_DES_ERR BIT(1) /* TX Descriptor Error */
63 /* Wt mac ad0 */
77 /* W mac 15_0 bus */
80 /* W mac 47_16 bus */
154 /* MAC force mode */
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/linux-6.12.1/drivers/net/ethernet/faraday/
Dftgmac100.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2009-2011 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
11 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
48 /* Min number of tx ring entries before stopping queue */
54 /* For NC-SI to register a fixed-link phy device */
76 /* Tx ring */
100 struct clk *clk; member
103 struct clk *rclk;
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/linux-6.12.1/arch/arm64/boot/dts/st/
Dstm32mp253.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
11 compatible = "arm,cortex-a35";
14 enable-method = "psci";
15 power-domains = <&CPU_PD1>;
16 power-domain-names = "psci";
20 arm-pmu {
23 interrupt-affinity = <&cpu0>, <&cpu1>;
27 CPU_PD1: power-domain-cpu1 {
28 #power-domain-cells = <0>;
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/linux-6.12.1/drivers/net/ethernet/nxp/
Dlpc_eth.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <linux/clk.h>
23 #include <linux/soc/nxp/lpc32xx-misc.h>
25 #define MODNAME "lpc-eth"
35 * Ethernet MAC controller Register offsets
317 if (dev && dev->of_node) { in lpc_phy_interface_mode()
318 const char *mode = of_get_property(dev->of_node, in lpc_phy_interface_mode()
319 "phy-mode", NULL); in lpc_phy_interface_mode()
328 if (dev && dev->of_node) in use_iram_for_net()
329 return of_property_read_bool(dev->of_node, "use-iram"); in use_iram_for_net()
[all …]
/linux-6.12.1/drivers/net/ethernet/
Dethoc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2008 Avionic Design Development GmbH
6 * Copyright (C) 2008-2009 Avionic Design GmbH
8 * Written by Thierry Reding <thierry.reding@avionic-design.de>
11 #include <linux/dma-mapping.h>
13 #include <linux/clk.h>
64 #define MODER_NBO (1 << 8) /* no back-off */
133 /* TX buffer descriptor */
141 #define TX_BD_CRC (1 << 11) /* TX CRC enable */
145 #define TX_BD_READY (1 << 15) /* TX buffer ready */
[all …]
/linux-6.12.1/Documentation/networking/device_drivers/ethernet/stmicro/
Dstmmac.rst1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
27 Currently, this network device driver is for all STi embedded MAC/GMAC
32 DesignWare(R) Cores Ethernet MAC 10/100/1000 Universal version 3.70a
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/linux-6.12.1/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-ingenic.c1 // SPDX-License-Identifier: GPL-2.0
3 * dwmac-ingenic.c - Ingenic SoCs DWMAC specific glue layer
9 #include <linux/clk.h>
75 struct ingenic_mac *mac = plat_dat->bsp_priv; in ingenic_mac_init() local
78 if (mac->soc_info->set_mode) { in ingenic_mac_init()
79 ret = mac->soc_info->set_mode(plat_dat); in ingenic_mac_init()
89 struct ingenic_mac *mac = plat_dat->bsp_priv; in jz4775_mac_set_mode() local
92 switch (plat_dat->mac_interface) { in jz4775_mac_set_mode()
96 dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_MII\n"); in jz4775_mac_set_mode()
102 dev_dbg(mac->dev, "MAC PHY Control Register: PHY_INTERFACE_MODE_GMII\n"); in jz4775_mac_set_mode()
[all …]
Ddwmac-mediatek.c1 // SPDX-License-Identifier: GPL-2.0
79 struct clk *rmii_internal_clk;
103 /* list of clocks required for mac */
114 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0; in mt2712_set_interface()
115 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0; in mt2712_set_interface()
119 switch (plat->phy_mode) { in mt2712_set_interface()
133 dev_err(plat->dev, "phy interface not supported\n"); in mt2712_set_interface()
134 return -EINVAL; in mt2712_set_interface()
137 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val); in mt2712_set_interface()
144 struct mac_delay_struct *mac_delay = &plat->mac_delay; in mt2712_delay_ps2stage()
[all …]
/linux-6.12.1/drivers/net/ethernet/socionext/
Dsni_ave.c1 // SPDX-License-Identifier: GPL-2.0
3 * sni_ave.c - Socionext UniPhier AVE ethernet driver
5 * Copyright 2015-2017 Socionext Inc.
9 #include <linux/clk.h>
38 /* MAC Register Group */
39 #define AVE_TXCR 0x200 /* TX Setup */
41 #define AVE_RXMAC1R 0x208 /* MAC address (lower) */
42 #define AVE_RXMAC2R 0x20c /* MAC address (upper) */
51 #define AVE_TXDC 0x304 /* TX Descriptor Configuration */
69 #define AVE_TXDM_64 0x1000 /* Tx Descriptor Memory */
[all …]
/linux-6.12.1/drivers/net/ethernet/freescale/
Dfec.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC
8 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9 * (C) Copyright 2000-2001, Lineo (www.lineo.com)
23 #include <dt-bindings/firmware/imx/rsrc.h>
45 #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */
46 #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */
48 #define FEC_TXIC0 0x0f0 /* Tx Interrupt Coalescing for ring 0 */
49 #define FEC_TXIC1 0x0f4 /* Tx Interrupt Coalescing for ring 1 */
50 #define FEC_TXIC2 0x0f8 /* Tx Interrupt Coalescing for ring 2 */
[all …]
/linux-6.12.1/drivers/net/ethernet/qualcomm/emac/
Demac.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
18 #include "emac-mac.h"
19 #include "emac-phy.h"
20 #include "emac-sgmii.h"
84 mutex_lock(&adpt->reset_lock); in emac_reinit_locked()
90 mutex_unlock(&adpt->reset_lock); in emac_reinit_locked()
100 struct emac_adapter *adpt = netdev_priv(rx_q->netdev); in emac_napi_rtx()
101 struct emac_irq *irq = rx_q->irq; in emac_napi_rtx()
109 irq->mask |= rx_q->intr; in emac_napi_rtx()
[all …]
/linux-6.12.1/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
Dmain.h35 #define NTXRATE 64 /* # tx MPDUs rate is reported for */
37 /* Maximum wait time for a MAC suspend */
48 * Usage example, e.g. a three-bit field (bits 4-6):
52 * regval = R_REG(osh, &regs->regfoo);
55 * W_REG(osh, &regs->regfoo, regval);
58 (((unsigned)1 << (width)) - 1)
65 #define SW_TIMER_MAC_STAT_UPD 30 /* periodic MAC stats update */
67 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
76 #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
91 #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
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/linux-6.12.1/arch/arm64/boot/dts/freescale/
Dimx93.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx93-clock.h>
7 #include <dt-bindings/dma/fsl-edma.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/fsl,imx93-power.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx93-pinfunc.h"
17 interrupt-parent = <&gic>;
[all …]
/linux-6.12.1/drivers/net/ethernet/allwinner/
Dsun4i-emac.c4 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
15 #include <linux/clk.h>
34 #include "sun4i-emac.h"
36 #define DRV_NAME "sun4i-emac"
41 static int debug = -1; /* defaults above */;
73 struct clk *clk; member
108 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
110 if (db->speed == SPEED_100) in emac_update_speed()
112 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
[all …]
/linux-6.12.1/drivers/net/ethernet/broadcom/
Dbcm63xx_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
29 * hardware maximum rx/tx packet size including FCS, max mtu is
199 /* mac irq, rx_dma irq, tx_dma irq */
204 /* hw view of rx & tx dma ring */
208 /* allocated size (in bytes) for rx & tx dma ring */
253 /* dma channel id for tx */
256 /* number of dma desc in tx ring */
265 /* number of available descriptor for tx */
268 /* next tx descriptor avaiable */
[all …]
/linux-6.12.1/drivers/net/ethernet/mediatek/
Dmtk_eth_soc.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
5 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
6 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
16 #include <linux/clk.h>
24 #include <linux/pcs/pcs-mtk-lynxi.h>
34 static int mtk_msg_level = -1;
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
294 __raw_writel(val, eth->base + reg); in mtk_w32()
299 return __raw_readl(eth->base + reg); in mtk_r32()
[all …]
/linux-6.12.1/arch/arm/boot/dts/intel/socfpga/
Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]

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