ethernet/freescale/fec.h

1 /* SPDX-License-Identifier: GPL-2.0 */
5  *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
8  *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
9  *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
23 #include <dt-bindings/firmware/imx/rsrc.h>
45 #define FEC_ADDR_LOW		0x0e4 /* Low 32bits MAC address */
46 #define FEC_ADDR_HIGH		0x0e8 /* High 16bits MAC address */
48 #define FEC_TXIC0		0x0f0 /* Tx Interrupt Coalescing for ring 0 */
49 #define FEC_TXIC1		0x0f4 /* Tx Interrupt Coalescing for ring 1 */
50 #define FEC_TXIC2		0x0f8 /* Tx Interrupt Coalescing for ring 2 */
81 #define FEC_X_DES_ACTIVE_1	0x1e4 /* Tx descriptor active for ring 1 */
83 #define FEC_X_DES_ACTIVE_2	0x1ec /* Tx descriptor active for ring 2 */
95 #define RMON_T_PACKETS		0x204 /* RMON TX packet count */
96 #define RMON_T_BC_PKT		0x208 /* RMON TX broadcast pkts */
97 #define RMON_T_MC_PKT		0x20c /* RMON TX multicast pkts */
98 #define RMON_T_CRC_ALIGN	0x210 /* RMON TX pkts with CRC align err */
99 #define RMON_T_UNDERSIZE	0x214 /* RMON TX pkts < 64 bytes, good CRC */
100 #define RMON_T_OVERSIZE		0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
101 #define RMON_T_FRAG		0x21c /* RMON TX pkts < 64 bytes, bad CRC */
102 #define RMON_T_JAB		0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
103 #define RMON_T_COL		0x224 /* RMON TX collision count */
104 #define RMON_T_P64		0x228 /* RMON TX 64 byte pkts */
105 #define RMON_T_P65TO127		0x22c /* RMON TX 65 to 127 byte pkts */
106 #define RMON_T_P128TO255	0x230 /* RMON TX 128 to 255 byte pkts */
107 #define RMON_T_P256TO511	0x234 /* RMON TX 256 to 511 byte pkts */
108 #define RMON_T_P512TO1023	0x238 /* RMON TX 512 to 1023 byte pkts */
109 #define RMON_T_P1024TO2047	0x23c /* RMON TX 1024 to 2047 byte pkts */
110 #define RMON_T_P_GTE2048	0x240 /* RMON TX pkts > 2048 bytes */
111 #define RMON_T_OCTETS		0x244 /* RMON TX octets */
113 #define IEEE_T_FRAME_OK		0x24c /* Frames tx'd OK */
114 #define IEEE_T_1COL		0x250 /* Frames tx'd with single collision */
115 #define IEEE_T_MCOL		0x254 /* Frames tx'd with multiple collision */
116 #define IEEE_T_DEF		0x258 /* Frames tx'd after deferral delay */
117 #define IEEE_T_LCOL		0x25c /* Frames tx'd with late collision */
118 #define IEEE_T_EXCOL		0x260 /* Frames tx'd with excesv collisions */
119 #define IEEE_T_MACERR		0x264 /* Frames tx'd with TX FIFO underrun */
120 #define IEEE_T_CSERR		0x268 /* Frames tx'd with carrier sense err */
121 #define IEEE_T_SQE		0x26c /* Frames tx'd with SQE err */
122 #define IEEE_T_FDXFC		0x270 /* Flow control pause frames tx'd */
123 #define IEEE_T_OCTETS_OK	0x274 /* Octet count for frames tx'd w/o err */
170 #define FEC_ADDR_LOW		0x3c0 /* Low 32bits MAC address */
171 #define FEC_ADDR_HIGH		0x3c4 /* High 16bits MAC address */
309  * ENET with AVB IP can support up to 3 independent tx queues and rx queues.
344 /* The number of Tx and Rx buffers.  These are allocated from the page
353 #define FEC_ENET_RX_FRSIZE	(PAGE_SIZE - FEC_ENET_XDP_HEADROOM \
354 		- SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
410 /* Controller is ENET-MAC */
430  * frames not being transmitted until there is a 0-to-1 transition on
437  * - Two class indicators on receive with configurable priority
438  * - Two class indicators and line speed timer on transmit allowing
440  * - Additional DMA registers provisioned to allow managing up to 3
445  * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles).
453  * The wait-time-cycles is at least 6 clock cycles of the slower clock between
455  * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns
493  * standard. For the transmission, MAC supply two user registers to set
518 	/* Address of Rx and Tx buffers */
581 	/* rx queue number, in the range 0-7 */
605 	struct clk *clk_ipg;
606 	struct clk *clk_ahb;
607 	struct clk *clk_ref;
608 	struct clk *clk_enet_out;
609 	struct clk *clk_ptp;
610 	struct clk *clk_2x_txclk;
617 	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
674 	/* tx lpi eee mode */