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Searched +full:jh7110 +full:- +full:ispcrg (Results 1 – 6 of 6) sorted by relevance

/linux-6.12.1/Documentation/devicetree/bindings/media/
Dstarfive,jh7110-camss.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/starfive,jh7110-camss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jack Zhu <jack.zhu@starfivetech.com>
11 - Changhuang Liang <changhuang.liang@starfivetech.com>
14 The Starfive CAMSS ISP is a Camera interface for Starfive JH7110 SoC. It
15 consists of a VIN controller (Video In Controller, a top-level control unit)
20 const: starfive,jh7110-camss
25 reg-names:
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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dstarfive,jh7110-ispcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-ispcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 Image-Signal-Process Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-ispcrg
21 - description: ISP Top core
22 - description: ISP Top Axi
23 - description: NOC ISP Bus
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/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
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Djh7110-common.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7110.dtsi"
9 #include "jh7110-pinfunc.h"
10 #include <dt-bindings/gpio/gpio.h>
25 stdout-path = "serial0:115200n8";
33 gpio-restart {
34 compatible = "gpio-restart";
39 pwmdac_codec: audio-codec {
40 compatible = "linux,spdif-dit";
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/linux-6.12.1/Documentation/devicetree/bindings/phy/
Dstarfive,jh7110-dphy-rx.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive SoC JH7110 MIPI D-PHY Rx Controller
10 - Jack Zhu <jack.zhu@starfivetech.com>
11 - Changhuang Liang <changhuang.liang@starfivetech.com>
14 StarFive SoCs contain a MIPI CSI D-PHY based on M31 IP, used to
19 const: starfive,jh7110-dphy-rx
26 - description: config clock
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/linux-6.12.1/drivers/clk/starfive/
Dclk-starfive-jh7110-isp.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 Image-Signal-Process Clock Driver
5 * Copyright (C) 2022-2023 StarFive Technology Co., Ltd.
9 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/starfive,jh7110-crg.h>
17 #include "clk-starfive-jh7110.h"
70 top_rsts = devm_reset_control_array_get_shared(priv->dev); in jh7110_isp_top_rst_init()
72 return dev_err_probe(priv->dev, PTR_ERR(top_rsts), in jh7110_isp_top_rst_init()
81 unsigned int idx = clkspec->args[0]; in jh7110_ispclk_get()
84 return &priv->reg[idx].hw; in jh7110_ispclk_get()
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