bindings/phy/starfive%2Cjh7110-dphy-rx.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-dphy-rx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive SoC JH7110 MIPI D-PHY Rx Controller
10   - Jack Zhu <jack.zhu@starfivetech.com>
11   - Changhuang Liang <changhuang.liang@starfivetech.com>
14   StarFive SoCs contain a MIPI CSI D-PHY based on M31 IP, used to
19     const: starfive,jh7110-dphy-rx
26       - description: config clock
27       - description: reference clock
28       - description: escape mode transmit clock
30   clock-names:
32       - const: cfg
33       - const: ref
34       - const: tx
38       - description: DPHY_HW reset
39       - description: DPHY_B09_ALWAYS_ON reset
41   power-domains:
44   "#phy-cells":
48   - compatible
49   - reg
50   - clocks
51   - clock-names
52   - resets
53   - power-domains
54   - "#phy-cells"
59   - |
61       compatible = "starfive,jh7110-dphy-rx";
63       clocks = <&ispcrg 3>,
64                <&ispcrg 4>,
65                <&ispcrg 5>;
66       clock-names = "cfg", "ref", "tx";
67       resets = <&ispcrg 2>,
68                <&ispcrg 3>;
69       power-domains = <&aon_syscon 1>;
70       #phy-cells = <0>;