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Searched +full:jh7100 +full:- +full:clkgen (Results 1 – 7 of 7) sorted by relevance

/linux-6.12.1/arch/riscv/boot/dts/starfive/
Djh7100.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
12 compatible = "starfive,jh7100";
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
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/linux-6.12.1/Documentation/devicetree/bindings/clock/
Dstarfive,jh7100-audclk.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-audclk.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 Audio Clock Generator
10 - Emil Renner Berthing <kernel@esmil.dk>
14 const: starfive,jh7100-audclk
21 - description: Audio source clock
22 - description: External 12.288MHz clock
23 - description: Domain 7 AHB bus clock
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Dstarfive,jh7100-clkgen.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7100-clkgen.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 Clock Generator
10 - Geert Uytterhoeven <geert@linux-m68k.org>
11 - Emil Renner Berthing <kernel@esmil.dk>
15 const: starfive,jh7100-clkgen
22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
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/linux-6.12.1/Documentation/devicetree/bindings/hwmon/
Dstarfive,jh71x0-temp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/hwmon/starfive,jh71x0-temp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Emil Renner Berthing <kernel@esmil.dk>
18 - starfive,jh7100-temp
19 - starfive,jh7110-temp
28 clock-names:
30 - const: sense
31 - const: bus
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/linux-6.12.1/Documentation/devicetree/bindings/pinctrl/
Dstarfive,jh7100-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/starfive,jh7100-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7100 Pin Controller
10 Bindings for the JH7100 RISC-V SoC from StarFive Ltd.
15 interesting 2-layered approach to pin muxing best illustrated by the diagram
21 LCD output -----------------| |
22 CMOS Camera interface ------| |--- PAD_GPIO[0]
23 Ethernet PHY interface -----| MUX |--- PAD_GPIO[1]
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/linux-6.12.1/Documentation/devicetree/bindings/pwm/
Dopencores,pwm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - William Qiu <william.qiu@starfivetech.com>
14 mode, the PTC core generates binary signal with user-programmable low and
15 high periods. All PTC counters and registers are 32-bit.
18 - $ref: pwm.yaml#
23 - enum:
24 - starfive,jh7100-pwm
25 - starfive,jh7110-pwm
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/linux-6.12.1/drivers/clk/starfive/
Dclk-starfive-jh7100.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7100 Clock Generator Driver
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/starfive-jh7100.h>
18 #include "clk-starfive-jh71x0.h"
273 unsigned int idx = clkspec->args[0]; in jh7100_clk_get()
276 return &priv->reg[idx].hw; in jh7100_clk_get()
279 return priv->pll[idx - JH7100_CLK_PLL0_OUT]; in jh7100_clk_get()
281 return ERR_PTR(-EINVAL); in jh7100_clk_get()
290 priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7100_CLK_PLL0_OUT), GFP_KERNEL); in clk_starfive_jh7100_probe()
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