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/linux-6.12.1/Documentation/devicetree/bindings/arm/omap/
Dcrossbar.txt4 time, so they have to be muxed to the irq-controller appropriately.
10 - compatible : Should be "ti,irq-crossbar"
11 - reg: Base address and the size of the crossbar registers.
12 - interrupt-controller: indicates that this block is an interrupt controller.
13 - ti,max-irqs: Total number of irqs available at the parent interrupt controller.
14 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
15 - ti,reg-size: Size of a individual register in bytes. Every individual
17 - ti,irqs-reserved: List of the reserved irq lines that are not muxed using
18 crossbar. These interrupt lines are reserved in the soc,
23 - ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
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/linux-6.12.1/drivers/irqchip/
Dirq-crossbar.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/irqchip/irq-crossbar.c
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
16 #define IRQ_FREE -1
17 #define IRQ_RESERVED -2
18 #define IRQ_SKIP -3
22 * struct crossbar_device - crossbar device description
47 writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); in crossbar_writel()
52 writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); in crossbar_writew()
57 writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); in crossbar_writeb()
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Dirq-nvic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/irq/irq-nvic.c
5 * Copyright (C) 2008 ARM Limited, All Rights Reserved.
9 * ARMv7-M CPUs (Cortex-M3/M4)
33 * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
34 * 16 irqs.
36 #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
43 irq_hw_number_t hwirq = (icsr & V7M_SCB_ICSR_VECTACTIVE) - 16; in nvic_handle_irq()
76 unsigned int irqs, i, ret, numbanks; in nvic_of_init() local
85 return -ENOMEM; in nvic_of_init()
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Dirq-pruss-intc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PRU-ICSS INTC IRQChip driver for various TI SoCs
5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - http://www.ti.com/
9 * Suman Anna <s-anna@ti.com>
24 * Number of host interrupts reaching the main MPU sub-system. Note that this
57 /* CMR register bit-field macros */
62 /* HMR register bit-field macros */
67 /* HIPIR register bit-fields */
74 * struct pruss_intc_map_record - keeps track of actual mapping state
84 * struct pruss_intc_match_data - match data to handle SoC variations
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/linux-6.12.1/arch/powerpc/platforms/powernv/
Dpci-cxl.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2014-2016 IBM Corp.
7 #include <misc/cxl-base.h>
8 #include <asm/pnv-pci.h>
15 struct pci_controller *hose = pci_bus_to_host(dev->bus); in pnv_phb_to_cxl_mode()
16 struct pnv_phb *phb = hose->private_data; in pnv_phb_to_cxl_mode()
22 return -ENODEV; in pnv_phb_to_cxl_mode()
26 rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number); in pnv_phb_to_cxl_mode()
28 dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n"); in pnv_phb_to_cxl_mode()
30 dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc); in pnv_phb_to_cxl_mode()
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/linux-6.12.1/include/linux/mfd/
Dintel_soc_pmic_mrfld.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2019 Intel Corporation. All rights reserved.
50 /* Level 1 IRQs */
60 /* Level 2 IRQs: power button */
64 /* Level 2 IRQs: ADC */
71 /* Level 2 IRQs: charger */
/linux-6.12.1/Documentation/devicetree/bindings/interrupt-controller/
Dti,pruss-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI PRU-ICSS Local Interrupt Controller
10 - Suman Anna <s-anna@ti.com>
13 Each PRU-ICSS has a single interrupt controller instance that is common
22 The property "ti,irqs-reserved" is used for denoting the connection
30 through 19) are connected to new sub-modules within the ICSSG instances.
32 This interrupt-controller node should be defined as a child node of the
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/linux-6.12.1/arch/mips/dec/
Dint-handler.S1 /* SPDX-License-Identifier: GPL-2.0 */
12 * Rewritten extensively for controller-driven IRQ support
50 * 3) Linux only thinks in terms of all IRQs on or all IRQs
51 * off, nothing in between like BSD spl() brain-damage.
53 * Furthermore, the IRQs on the DECstations look basically (barring
54 * software IRQs which we don't use at all) like...
59 * -------- ------
72 * -------- ------
77 * 4 Reserved
79 * 6 Reserved
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/linux-6.12.1/kernel/irq/
Dmatrix.c1 // SPDX-License-Identifier: GPL-2.0
41 * irq_alloc_matrix - Allocate a irq_matrix structure and initialize it
58 m->system_map = &m->scratch_map[matrix_size]; in irq_alloc_matrix()
60 m->matrix_bits = matrix_bits; in irq_alloc_matrix()
61 m->alloc_start = alloc_start; in irq_alloc_matrix()
62 m->alloc_end = alloc_end; in irq_alloc_matrix()
63 m->alloc_size = alloc_end - alloc_start; in irq_alloc_matrix()
64 m->maps = __alloc_percpu(struct_size(m->maps, alloc_map, matrix_size * 2), in irq_alloc_matrix()
65 __alignof__(*m->maps)); in irq_alloc_matrix()
66 if (!m->maps) { in irq_alloc_matrix()
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/linux-6.12.1/include/linux/amba/
Dbus.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
35 * Class 0x2-0x8,0xA and 0xD-0xD are presently reserved.
37 * Remaining CID bits stay as 0xb105-00d
44 * the amba_id->data pointer.
112 #define amba_get_drvdata(d) dev_get_drvdata(&d->dev)
113 #define amba_set_drvdata(d,p) dev_set_drvdata(&d->dev, p)
128 return -EINVAL; in __amba_driver_register()
149 #define amba_config(d) AMBA_CONFIG_BITS((d)->periphid)
150 #define amba_rev(d) AMBA_REV_BITS((d)->periphid)
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/linux-6.12.1/arch/mips/sgi-ip30/
Dip30-irq.c1 // SPDX-License-Identifier: GPL-2.0
3 * ip30-irq.c: Highlevel interrupt handling for IP30 architecture.
18 #include "ip30-common.h"
36 return -ENOSPC; in heart_alloc_int()
50 pending = heart_read(&heart_regs->isr); in ip30_error_irq()
51 mask = heart_read(&heart_regs->imr[cpu]); in ip30_error_irq()
52 cause = heart_read(&heart_regs->cause); in ip30_error_irq()
59 /* Prevent any of the error IRQs from firing again. */ in ip30_error_irq()
60 heart_write(mask & ~(pending), &heart_regs->imr[cpu]); in ip30_error_irq()
62 /* Ack all error IRQs. */ in ip30_error_irq()
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/linux-6.12.1/drivers/net/ethernet/mellanox/mlx5/core/
Dpci_irq.h1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
2 /* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
21 char name[MLX5_MAX_IRQ_NAME - MLX5_MAX_IRQ_IDX_CHARS];
23 struct mutex lock; /* sync IRQs creations */
24 struct xarray irqs; member
34 return !strncmp("mlx5_sf", pool->name, strlen("mlx5_sf")); in mlx5_irq_pool_is_sf_pool()
Dirq_affinity.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2 /* Copyright (c) 2021, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
10 pool->irqs_per_cpu[cpu]--; in cpu_put()
15 pool->irqs_per_cpu[cpu]++; in cpu_get()
18 /* Gets the least loaded CPU. e.g.: the CPU with least IRQs bound to it */
22 int best_cpu = -1; in cpu_get_least_loaded()
26 /* CPU has zero IRQs on it. No need to search any more CPUs. */ in cpu_get_least_loaded()
27 if (!pool->irqs_per_cpu[cpu]) { in cpu_get_least_loaded()
33 if (pool->irqs_per_cpu[cpu] < pool->irqs_per_cpu[best_cpu]) in cpu_get_least_loaded()
36 if (best_cpu == -1) { in cpu_get_least_loaded()
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/linux-6.12.1/arch/powerpc/sysdev/
Dmsi_bitmap.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2006-2008, Michael Ellerman, IBM Corporation.
20 spin_lock_irqsave(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
22 offset = bitmap_find_next_zero_area(bmp->bitmap, bmp->irq_count, 0, in msi_bitmap_alloc_hwirqs()
23 num, (1 << order) - 1); in msi_bitmap_alloc_hwirqs()
24 if (offset > bmp->irq_count) in msi_bitmap_alloc_hwirqs()
27 bitmap_set(bmp->bitmap, offset, num); in msi_bitmap_alloc_hwirqs()
28 spin_unlock_irqrestore(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
34 spin_unlock_irqrestore(&bmp->lock, flags); in msi_bitmap_alloc_hwirqs()
35 return -ENOMEM; in msi_bitmap_alloc_hwirqs()
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/linux-6.12.1/arch/arc/include/asm/
Dirqflags-arcv2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
12 #define STATUS_AD_BIT 19 /* Disable Align chk: core supports non-aligned */
39 * Linux by default runs at 1, priority 0 reserved for NMI style interrupts
56 * Save IRQ state and disable IRQs
76 * Unconditionally Enable IRQs
89 * Unconditionally Disable IRQs
/linux-6.12.1/drivers/input/serio/
Di8042-io.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 * IRQs.
19 /* defined in include/asm-arm/arch-xxx/irqs.h */
64 * bad things. Because of this the region is always reserved on such boxes. in i8042_platform_init()
68 return -ENODEV; in i8042_platform_init()
72 return -EBUSY; in i8042_platform_init()
/linux-6.12.1/drivers/net/fddi/
Ddefza.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* FDDI network adapter driver for DEC FDDIcontroller 700/700-C devices.
36 #define FZA_RESET_CLR 0x0000 /* run self-test and return to work */
43 #define FZA_EVENT_NXM_ERR 0x0080 /* non-existent memory access error;
45 * unsupported partial-word accesses
93 #define FZA_HALT_HOST 0x01 /* host-directed HALT */
95 #define FZA_HALT_NXM 0x03 /* adapter non-existent memory ref. */
102 #define FZA_TEST_FATAL 0x00 /* self-test catastrophic failure */
106 #define FZA_TEST_SRAM_STUCK1 0x04 /* SRAM stuck-at range 1 */
107 #define FZA_TEST_SRAM_STUCK2 0x05 /* SRAM stuck-at range 2 */
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/linux-6.12.1/drivers/vdpa/solidrun/
Dsnet_main.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2022-2023 SolidRun
7 * Author: Alvaro Karsz <alvaro.karsz@solid-run.com>
42 if (likely(snet->cb.callback)) in snet_cfg_irq_hndlr()
43 return snet->cb.callback(snet->cb.private); in snet_cfg_irq_hndlr()
52 if (likely(vq->cb.callback)) in snet_vq_irq_hndlr()
53 return vq->cb.callback(vq->cb.private); in snet_vq_irq_hndlr()
60 struct psnet *psnet = snet->psnet; in snet_free_irqs()
64 /* Which Device allcoated the IRQs? */ in snet_free_irqs()
66 pdev = snet->pdev->physfn; in snet_free_irqs()
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/linux-6.12.1/drivers/misc/cxl/
Dirq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
14 #include <misc/cxl-base.h>
28 ctx->dsisr = dsisr; in schedule_cxl_fault()
29 ctx->dar = dar; in schedule_cxl_fault()
30 schedule_work(&ctx->fault_work); in schedule_cxl_fault()
38 dsisr = irq_info->dsisr; in cxl_irq_psl9()
39 dar = irq_info->dar; in cxl_irq_psl9()
43 pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar); in cxl_irq_psl9()
46 pr_devel("CXL interrupt: Scheduling translation fault handling for later (pe: %i)\n", ctx->pe); in cxl_irq_psl9()
51 return cxl_ops->handle_psl_slice_error(ctx, dsisr, in cxl_irq_psl9()
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/linux-6.12.1/drivers/mfd/
Dintel_soc_pmic_bxtwc.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2015-2017, 2022 Intel Corporation. All rights reserved.
144 .irqs = bxtwc_regmap_irqs,
153 .irqs = bxtwc_regmap_irqs_pwrbtn,
162 .irqs = bxtwc_regmap_irqs_tmu,
171 .irqs = bxtwc_regmap_irqs_bcu,
180 .irqs = bxtwc_regmap_irqs_adc,
189 .irqs = bxtwc_regmap_irqs_chgr,
198 .irqs = bxtwc_regmap_irqs_crit,
284 return -EINVAL; in regmap_ipc_byte_reg_read()
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Dtps65090.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
55 .name = "tps65090-pmic",
58 .name = "tps65090-charger",
61 .of_compatible = "ti,tps65090-charger",
66 /* INT1 IRQs*/
88 /* INT2 IRQs*/
125 .irqs = tps65090_irqs,
167 struct tps65090_platform_data *pdata = dev_get_platdata(&client->dev); in tps65090_i2c_probe()
172 if (!pdata && !client->dev.of_node) { in tps65090_i2c_probe()
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/linux-6.12.1/arch/m68k/q40/
Dq40ints.c30 * Q40 IRQs are defined as follows:
31 * 3,4,5,6,7,10,11,14,15 : ISA dev IRQs
32 * 16-31: reserved
48 unsigned int irq = data->irq; in q40_irq_startup()
56 /* FIXME return -ENXIO; */ in q40_irq_startup()
98 master_outb(1, EXT_ENABLE_REG); /* ISA IRQ 5-15 */ in q40_init_IRQ()
117 /* simply alternate the ampl (128-SVOL)-(128+SVOL)-..-.. at 200Hz */ in q40_mksound()
137 unsigned char sval=(sound_ticks & 1) ? 128-SVOL : 128+SVOL; in q40_timer_int()
138 sound_ticks--; in q40_timer_int()
163 master_outb(-1, FRAME_CLEAR_REG); in q40_sched_init()
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/linux-6.12.1/arch/powerpc/platforms/ps3/
Dspu.c1 // SPDX-License-Identifier: GPL-2.0-only
28 * enum spe_type - Type of spe to create.
40 * struct spe_shadow - logical spe shadow register area.
42 * Read-only shadow of spe registers.
50 u8 padding_0158[0x0610-0x0158];
52 u8 padding_0618[0x0620-0x0618];
54 u8 padding_0628[0x0800-0x0628];
56 u8 padding_0808[0x0810-0x0808];
58 u8 padding_0818[0x0c00-0x0818];
60 u8 padding_0c08[0x0f00-0x0c08];
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/linux-6.12.1/arch/arm/mach-tegra/
Dhotplug.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * All Rights Reserved
5 * Copyright (c) 2010, 2012-2013, NVIDIA Corporation. All rights reserved.
34 * platform-specific code to shutdown a CPU
36 * Called with IRQs disabled
/linux-6.12.1/Documentation/arch/x86/i386/
DIO-APIC.rst1 .. SPDX-License-Identifier: GPL-2.0
4 IO-APIC
9 Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC',
12 IO-APIC, interrupts from hardware will be delivered only to the
16 multiple IO-APICs. Multiple IO-APICs are used in high-end servers to
20 usually worked around by the kernel. If your MP-compliant SMP board does
21 not boot Linux, then consult the linux-smp mailing list archives first.
23 If your box boots fine with enabled IO-APIC IRQs, then your
28 0: 1360293 IO-APIC-edge timer
29 1: 4 IO-APIC-edge keyboard
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